超高速集成电路的设计-D型触发器

随着电子计算机的迅速发展,需要超高速的大规模集成电路。为了科研和生产的需要,这次毕业实践进行了D型触发器(ECL)的设计、研制与应用方面的工作,本文仅讨论D型触发器(ECL)的设计。该触发器为ECL电路系列,它具有速度快,集成度高等优点,所设计的D型触发器时延达到了3～4亳徽秒,功耗150亳瓦。单D电路的功能相当于由六个单门组成的维持阻塞型触发器,有晶体管41只,电阻38个,共79个元件。所设计的D型触发器为4D,单元版图为2D-FF,经二次布线构成4D-FF,集成度相当于25个门,晶体管164只,电阻142个,共306个元件。     

ECL集成电路的四值接口技术

本文介绍了适用于多值ECL电路设计的差动电流开关理论。在该理论中,分别用开关变量和四值信号变量来描写ECL电路中差动晶体管对的开关状态和信号,并引入此两类变量之间的联结运算,以描写电路内部开关元件与信号的相互作用过程。基于该理论,本文对两种接口电路2-4编码器和4-2译码器进行了设计。应用SPICE程序对设计电路的计算机模拟表明,两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。由于该接口电路具有与二值电路兼容的集成工艺、电源设备、逻辑级差和瞬态特性,因此它可用作现有二值ECL集成电路的输入输出接口,从而达到减少芯片的引脚数和片间连接的目的。     

数字交叉式转换开关AD8150

AD8150是ANALOG DEVICES公司生产的数字交叉式转换开关，它具有1Gbps的高数据通过率、低功耗、完全差动、PECL和ECL兼容等优良性能。文中介绍了AD8150的主要特点、引脚功能、内部电路和工作原理。最后介绍了它的接口设计方法。     

基于开关信号理论的四值ECL电路

从一个有效的多值代数系统应能反映多值电路中的物理过程的这一原则出发,本文提出了一组可以描写多值ECL电路中信号与开关元件间相互作用的运算。讨论了这些运算的物理对应及有关性质,并由此建立了适用于ECL电路的开关信号理论。本文设计了若干基本四值ECL电路,用SPICE程序模拟证明了它们均具有正确的逻辑功能与理想的DC特性。     

基于多值逻辑的高速ECL模糊控制表查询电路

该文指出了硬件实现模糊控制表查询电路存在结构复杂、用数字式实现时设计困难等问题,提出了将模糊控制表转换为多值K图,利用K图从开关级设计模糊控制表查询电路的方法,并用此方法具体设计了一个论域元素个数为5的ECL模糊控制表查询电路。从设计实例看,该文提出的设计方法简单易行,而设计的ECL查询电路具有结构简单和高速推理的优点。     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

自主化全电子信号机控制单元的设计与研究

设计和实现全电子计算机联锁中的信号机控制单元驱动和采集信号机信息。全电子信号机控制单元设计为二乘二取二架构,在硬件设计中,单元分为主从CPU模块、监控CPU模块、信号机接口模块、电源模块和复位模块等六种功能电路。其中,信号机接口模块中的信号机点灯电路采用机械开关和电子开关,异构的驱动设计有效避免共模错误。遵循EN50129标准,软件设计为初始化、通信控制、应用程序、状态机计算和驱动五个功能模块。然后,对全电子信号机控制单元的可靠性进行了分析,结果表明单元的可靠性能够满足铁路信号系统的安全需求。最后搭建了测试环境,对全电子信号机控制单元进行硬件、软件和集成测试,验证了单元的可用性和稳定性。     

低电压低功耗ECL电路设计

首先指出了 ECL电路随着集成度和速度的提高 ,存在着功耗太大的问题 ,进而提出了采用低电压电源以降低功耗 ,为此发展了将串联开关转换成并联开关的技术 ,保证了电路能在低电压下正常工作 ,并由此实现了适合于低电压工作的 ECL电路的开关级设计。从对设计的电路进行的计算机模拟结果表明 ,采用文中提出的并联开关技术设计的电路 ,在电源电压为 -2 .5 V时 ,不仅具有正确的逻辑功能和较高的工作速度 ,且比采用-5 .0 V电源的电路节约了 80 %以上的功耗     

电流开关结构提高 LSI 逻辑速度

大规模集成电路逻辑设计者在电路尺寸和性能方面从事的逻辑结构却不是用作大规模集成电路的。原先设计的 DTL、TTL 和 ECL 结构是作为门功能的,而不是作为高集成功能的。这些电路结构的功率/延迟乘积约为80微微焦耳;典型的8毫微秒传播延迟的 TTL 门功耗约10毫瓦;而 ECL 门是0.9毫微秒,约90毫瓦。     

超高速低功耗ECL予置分频器研究

本文介绍一个÷5/6低功耗ECL予置分频器的设计,从降低电源电压,减小内部逻辑摆幅和寄生电容等几方面讨论了提高电路高速低功耗特性的途径。该电路采用串联电源电压结构,内部电路在-2.5V～-2.7V电源电压下工作。电路功耗仅为具有相同功能的普通ECL电路的1/6。采用3μm设计规则的氧化物隔离等平面S型双极工艺。发射极条实际尺寸2μm×9μm,晶体管f_i为3.2GHz。室温下典型功耗75mW,最高M作频率大于900MHz。     

一种基于NAND Flash固态硬盘的坏块管理方法

基于NAND Flash的固态硬盘存在坏块,坏块无法用于存储数据,需要对其进行管理。每个块用1位信息与之对应建立坏块表,根据坏块表建立逻辑块转变为物理块表,一个逻辑块对应多个不同的物理块。逻辑块转变为物理块表可排除上层对于坏块的操作,保证了数据存储的安全性和可靠性。     

An Improved Non‐CSD 2‐Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two‐bit common subexpression (CS) can be located recursively in a non‐canonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.     

FRS: Replication Driver Layer-Based Data Replication System on FreeBSD

Data replication is a key way to design a disaster tolerance system.This paper presents a replication driver layer-based data replication system on FreeBSD(FRS).The system is embedded into the replication device driver layer,does not depend on specific storage devices and logical volume manager,and can achieve replication on data block level.The design considerations and decisions in defining FRS are described in detail.     

Digital simulation of an automotive multiplexing wiring system

A digital simulator for an automotive multiplexing system has been developed and tested. The basic architecture and logical flow and block diagrams are described. Some results of the simulation are given. The contention scheme was found to work successfully in the simulator, and the outputs were found to be ordered in the same manner as expected by the requirements of the protocol. The network traffic and its effect on the latency index has also been studied. The simulator has provisions to incorporate alternate message retrial schemes and to test alternative strategies of the tasks. It is flexible enough so that the effects of noise and other nonideal phenomena can be incorporated. It is concluded that this simulator is a useful design/development tool due to its flexibility in testing alternative design strategies     

功能险象的简化快速算法研究

文中利用参与逻辑函数和逻辑函数余式的理论,得到了一系列重要的规律,使用导出的等效二变量逻辑余式状态变化过程可对功能冒险精确定位,避免了繁琐沉重的计算,为数字电路和计算机设计奠定了基础。     

Adder design using 5-input majority gate in a novel “Multilayer Gate Design Paradigm” for Quantum Dot Cellular Automata Circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.     

On routing in large WDM networks

An important problem in WDM network design is to construct a logical topology and determine an optimal routing over that topology. Mixed Integer Linear Program (MILP) formulations to generate optimal solutions for this problem have been presented. Such formulations are computationally intractable, even for moderate sized networks. A standard approach is to decouple the problem of logical topology design and the problem of routing the traffic on this logical topology. Heuristics for finding the logical topology exist and a straight-forward linear program (LP), based on the node-arc formulation can be used to solve the routing problem over a given logical topology. We have found that such LP formulations become computationally infeasible for large networks. In this paper, we present a new formulation, based on the arc-chain representation, for optimally routing the specified traffic over a given logical topology to minimize the congestion of the network. We have used the revised simplex method incorporating an implicit column generation technique, and exploited the special Generalized Upper Bounding structure as well as the possibility of eta-factorization for efficiently updating the dual variables and finding the solution. Experimental results on a number of networks demonstrate the suitability of this approach.     

802.11b中卷积码和Viterbi译码的FPGA设计实现

卷积码是一种重要的信道纠错编码方式,其纠错性能通常优于分组码,目前(2,1,6)卷积码已广泛应用于无线通信系统中,Viterbi译码算法能最大限度地发挥卷积码的纠错性能。阐述了802.11b中卷积码的编码及其Viterbi译码方法,给出了编译码器的设计方法,并利用Verilog HDL硬件描述语言完成编译码器的FPGA实现。使用逻辑分析仪,在EP2C5T144C8芯片上完成了编译码器的硬件调试。     

Strategies for optimal logical topology design and traffic grooming

Traffic grooming techniques are used to combine low-speed data streams onto high-speed lightpaths with the objective of minimizing the network cost, or maximizing the network throughput. In this article, we present a complete suite of efficient Integer Linear Program (ILP) formulations for logical topology design and traffic grooming on mesh WDM networks. Our formulations can be easily modified to implement different objective functions and, contrary to previous formulations, our ILP formulation can be used to generate optimal solutions for practical sized networks with hundreds of requests. Our first set of formulations addresses the complete logical topology design traffic grooming problem, including RWA and traffic routing. The second set uses the simplifying assumption that RWA is not an issue. The last two sets address optimal traffic grooming alone, where the logical topology is already specified. We have studied these formulations, using simulation with networks having up to 30 nodes, and with hundreds and, in some cases, over a thousand low-speed data streams and have shown that the formulations are able to generate optimal solutions within a reasonable amount of time.     

IEEE802.15.4中AES-CCM协议的扩展指令集实现

该文在高级加密标准(AES)快速算法的基础上,设计了一组基于可配置处理器NiosⅡ上的扩展指令,用于IEEE802.15.4标准媒体访问控制层中基于AES算法的计数器模式和密码分组链接消息验证码(AES-CCM)协议的硬件加速.该文首先推导出快速算法中用于轮变换的查找表与S盒的逻辑关系,然后通过复合域变换方法用硬件电路实现S盒的计算,从而消除了支撑扩展指令集的硬件逻辑对片上存储空间的消耗.同时给出该协议基于查表法的扩展指令集和协处理器的设计方案,并在EP2C35芯片上进行实现和对比.该方案仅消耗223个逻辑单元(LE),吞吐量为668.7 kbps,时钟周期数比软件算法加速174.6倍,芯片面积仅为协处理器方案的9.5％,显著降低了无线传感网节点设备的成本和功耗.