金属沾污对超薄栅氧(2.5nm)特性的影响

采用可控的金属沾污程序,最大金属表面浓度控制在1012cm-2数量级,来模拟清洗工艺最大可能金属沾污表面浓度.利用斜坡电流应力和栅注入方式测量本征电荷击穿来评估超薄栅氧特性和金属沾污效应.研究了金属锆和钽沾污对超薄栅氧完整性的影响.实验结果表明金属锆沾污对超薄栅氧完整性具有最严重危害;金属钽沾污的栅氧发生早期击穿现象,而金属铝沾污对超薄栅氧完整性没有明显影响.     

金属沾污对超薄栅氧(2. 5nm)特性的影响

采用可控的金属沾污程序 ,最大金属表面浓度控制在 10 1 2 cm- 2数量级 ,来模拟清洗工艺最大可能金属沾污表面浓度 .利用斜坡电流应力和栅注入方式测量本征电荷击穿来评估超薄栅氧特性和金属沾污效应 .研究了金属锆和钽沾污对超薄栅氧完整性的影响 .实验结果表明金属锆沾污对超薄栅氧完整性具有最严重危害 ;金属钽沾污的栅氧发生早期击穿现象 ,而金属铝沾污对超薄栅氧完整性没有明显影响 .     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

This paper reports the impacts of the pre-gate oxide cleaning on the statistic fluctuations of a deep submicron CMOS devices’ saturation current, leakage current, threshold voltage, and gate oxide integrity (GOI) in detail. These statistic distributions are based on a foundry’s batch production line. This study concludes that the pre-gate oxide hot water clean enhances silicon surface’s micro-roughness and stress effects, thus are responsible to the higher fluctuations of devices performance distributions. Similar results were found in the GOI of the thin gate oxide. The micro-roughness and stress effects of silicon surface were evaluated systematically through atom force microscope (AFM) and thin film stress measurement system, and their mechanisms are interpreted comprehensively with schematic models.     

Roles of sidewall oxidation in the devices with shallow trenchisolation

The effects of sidewall sacrificial and sidewall oxidations on the characteristics of devices with shallow trench isolation (STI) have been investigated. We found that sidewall sacrificial and sidewall oxidations significantly affected junction leakage and gate oxide integrity (GOI). The sidewall sacrificial oxidation was shown to reduce oxidation-induced stresses and make the trench top corner more rounded. This reduced stress and more rounded top corner led to much improved junction leakage and GOI. These results clearly show that the sidewall sacrificial oxidation is worth using, although it adds complexity to the STI process     

Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2 V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.     

Effect of FN stress and gate-oxide breakdown on high-frequency noise characteristics in deep-submicrometer nMOSFETs

The impact of Fowler-Nordheim (FN) stress and oxide breakdown on high-frequency noise characteristics in 0.18 /spl mu/m nMOSFET has studied. Noise characteristics of the devices at different leakage levels and breakdown hardness are compared. The results have shown a strong dependence of degradation of noise parameter on the gate leakage. The degradation mechanisms are analyzed by extraction of the channel and gate noise using a noise equivalent circuit model. It has been found that gate shot noise, which is commonly ignored in the as-processed nMOSFET, plays a dominant role in determining the high frequency noise in the post-oxide breakdown nMOSFET. The effect of FN stress and oxide breakdown is negligible.     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

Origin of positive charge generated in thin SiO2 filmsduring high-field electrical stress

The characteristics of electron capture in a 131-Å silicon dioxide after hot-hole injection have been studied, which have been compared with those after high-field Fowler-Nordheim (FN) electron injection. After hole injection from the silicon substrate into the oxide, positive charges accumulated in the oxide and electrons could be captured even at low oxide fields only under the positive gate polarity. The charge centroid of the captured electrons was near the substrate-SiO ₂ interface. The low-field electron capture can be explained based on the electron tunneling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO₂ interface. In order to investigate the initial stage of the oxide degradation due to high-field FN stress, electrons were injected from the gate and the charge fluence was selected to be -1.0 C/cm². After the high-field stress, positive charges appeared in the oxide and electrons were captured only under the positive gate polarity by the positive charge and neutral trap centers, which were distributed near the interface. These facts are explained on the basis of the model describing that hole injection and trapping are the dominant causes for the generation of the positive charge centers during high-field FN stress     

多晶硅后热退火引起SiO_2栅介质可靠性下降的原因分析及其抑制方法

实验研究表明 ,多晶硅后的高温退火明显引起热 Si O2 栅介质击穿电荷降低和 FN应力下电子陷阱产生速率增加 .采用 N2 O氮化则可完全消除这些退化效应 ,而且氮化栅介质性能随着退火时间增加反而提高 .分析认为 ,高温退火促使多晶硅内 H扩散到 Si O2 内同 Si— O应力键反应形成 Si— H是多晶硅后 Si O2 栅介质可靠性退化的主要原因 ;氮化抑制退化效应是由于 N “缝合”了 Si O2 体内的 Si— O应力键缺陷 .     

Gate oxide integrity on ITOX-SIMOX substrates and influence of testdevice geometry on characterization

The integrity of gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal-thermal-oxidation (ITOX) process, so-called ITOX-SIMOX substrates, was evaluated, and the influence of test device geometry on the characterization was investigated. Characterization of time-dependent dielectric breakdown (TDDB) was performed for a gate oxide of 8.6-nm thick using lateral test devices. Experimental results show considerable influence of gate electrode geometry on the gate oxide integrity (GOI) characteristics. This can be explained by a model that includes a lateral parasitic resistance in the superficial Si layer beneath the gate electrode. Based on analysis using this model, a test device with a small gate array was proposed to reduce the influence of lateral parasitic resistance, and the advantage of the device was verified     

GaAs MESFET's on a truly insulating buffer layer: demonstration ofthe GaAs on insulator technology

We demonstrate for the first time a GaAs on insulator (GOI) technology, with aluminum oxide (Al₂O₃) formed by the wet oxidation of AlAs as the insulating buffer layer. The insulating buffer gives excellent charge control and eliminates substrate leakage current. The first results of GOI technology include 1.5-μm gate length GOI MESFET's with f_τ=9 GHz and f_max=45 GHz     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.     

超薄栅MOS结构恒压应力下的直接隧穿弛豫谱

随着器件尺寸的迅速减小 ,直接隧穿电流将代替 FN电流而成为影响器件可靠性的主要因素 .根据比例差值算符理论和弛豫谱技术 ,针对直接隧穿应力下超薄栅 MOS结构提出了一种新的弛豫谱——恒压应力下的直接隧穿弛豫谱 (DTRS) .该弛豫谱保持了原有弛豫谱技术直接、快速和方便的优点 ,能够分离和表征超薄栅 MOS结构不同氧化层陷阱 ,提取氧化层陷阱的产生 /俘获截面、陷阱密度等陷阱参数 .直接隧穿弛豫谱主要用于研究直接隧穿注入的情况下超薄栅 MOS结构中陷阱的产生和复合 ,为超薄栅 MOS结构的可靠性研究提供了一强有力工具 .     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.     

Damage-Less Sputter Depositions by Plasma Charge Trap for Metal Gate Technologies

Damage-free sputter deposition process has been developed for metal gate complementary metal-oxide-semiconductor technology. A plasma charge trap (PCT) was introduced in order to eliminate high-energy particle bombardment during sputter deposition processes. Molybdenum (Mo)-gated PMOSFETs were fabricated using a conventional gate-first process. It is shown that the PCT technology yields excellent characteristics in current drivability, as well as in gate oxide integrity (GOI) such as gate leakage current and charge-to-breakdown$(Q_BD)$. The metal gate was also applied to a nonvolatile memory (NVM), which would require most stringent damage control, and good retention characteristics were demonstrated.     

Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V_t in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.