Theoretical and experimental characteristics of the insulated-gatethyristor (IGTH)

A Insulated-Gate Thyristor (IGTH) design consisting of square cells with high density of MOS channels modulating the resistance of the base region of the NPN transistor of the thyristor structure is described. The on-state characteristics of IGTH structures including the effect of the lateral parasitic bipolar transistor are studied with the help of numerical device simulations and are analytically modeled by simple analytical equations. The variation of IGTH characteristics with temperature and electron-irradiation dose is experimentally studied and the behavior is explained with the help of analytical equations. The modeling results were found to be in good agreement with experimental results obtained on many lots of 600 V-1200 V Insulated-Gate Thyristors (IGTH) fabricated with an active area of 1.3 mm²-0.35 cm². The analytical models developed can also be applied to design and predict the characteristics of other MOS-gated thyristor structures     

Lateral complementary transistor structure for the simultaneous fabrication of functional blocks

Heretofore, the schemes for fabricating a complementary transistor structure in a monolithic functional block entailed either some additional, difficult-to-control processing steps or a sacrifice in isolation of the collector regions of one type of transistor. This paper describes an isolated p-n-p transistor structure fabricated by the same technique used for the conventional all n-p-n transistor functional block without any additional processing steps. The basic p-n-p transistor has a lateral structure. During the p-type base diffusion of the n-p-n transistor, two concentric p-type regions at close distance are selectively diffused into an isolated n- type region such as that used for the collector of an n-p-n transistor. The center p-type diffused region forms the emitter and the outer ring forms the collector. The n-type spacing between these two regions serves as the base. The current gain of this transistor is not high, typically around unity. However, by amplifying the collector current of the p-n-p transistor with an n-p-n transistor, the composite transistor acts like a high gain p-n-p transistor and the composite current gain can be made comparable to that of the n-p-n transistor in the same functional block. The lateral complementary transistor has been used extensively and successfully for the fabrication of linear functional blocks such as those used in the Advanced Minuteman Program.     

An AlGaAs/GaAs heterostructure-emitter bipolar transistor

An AlGaAs/GaAs heterostructure-emitter bipolar transistor using separate carrier injection and confinement is discussed. A common-emitter current gain of 28 with BV_CEO=15 V was obtained at a base doping level of 1×10¹⁹/cm³ . No spacer layer was inserted in the structure. This transistor combines the merits of homojunction transistors and regular heterostructure bipolar transistors (HBTs) and is simple to fabricate     

A new lateral MOS-controlled thyristor

A lateral MOS-controlled thyristor (LMCT) structure that uses an MOS gate to turn it both on and off is presented. The device structure offers improved maximum turn-off current capability and forward voltage drop. The former is achieved by using a DMOS transistor and a parasitic vertical p-n-p transistor, while the latter is achieved by eliminating a parasitic lateral p-n-p transistor in the conventional structure. The device utilizes the resurf technique to achieve high area efficiency, breakdown voltage, and reliability. Devices that have more than 250-V forward blocking capability were fabricated in dielectrically isolated silicon tubs using the standard bipolar-CMOS-DMOS process     

Epitaxial V-groove bipolar integrated circuit process

A new four-mask "V-groove" process for the fabrication of bipolar integrated circuits has been developed. The process utilizes epitaxial ν/n⁺/n^-layers and anisotropic etching oflangle100ranglesilicon to eliminate the buried layer and isolation diffusions as well as the need for masking the base diffusion of the standard six-mask bipolar integrated circuit process, n-p-n transistor, resistor, and Schottky diode characteristics are equivalent to or exceed those of the standard process. A five-mask V-groove process provides improved lateral p-n-p transistors compared with the four-mask approach. The V-groove integrated circuit structure offers simpler processing, smaller isolation capacitances, lower parasitic collector resistances, larger packing densities, and higher junction breakdown voltages than standard bipolar integrated circuits without degradation of other properties.     

A new lateral anode switched thyristor (LAST) with currentsaturation and low turn-off time

A novel MOS-gate controlled thyristor, entitled lateral anode switched thyristor (LAST), which exhibits a high current saturation and a low turn-off time, is proposed and successfully fabricated. Experimental results show that the new LAST achieves a current saturation capability larger than 1200 A/cm² even at high anode voltages. The forward voltage drop of LAST is 1.2 V at 100 A/cm ² where 10 V was biased to the dual gates. The turn-off time of LAST without any lifetime-control process is 1.5 μs while that of LAST without p⁺ diverter is about 2.9 μs. Our experimental data indicates that the p⁺ diverter successfully diverts holes in the drift region during the turn-off and a turn-off time is considerably decreased in the proposed LAST. The LAST, where any trouble-some parasitic thyristor mechanism is eliminated, completely suppresses a latch-up and increases the maximum controllable current considerably     

A new Insulated-Gate Thyristor structure with turn-off achieved bycontrolling the base-resistance

A new Insulated-Gate Thyristor (IGTH) design for achieving high controllable current capability is described. The design consists of square cells with high density of MOS-channels modulating the resistance of the base region of the NPN transistor of the thyristor structure. The diagonal regions between the square cells is used as the turn-on regions while the other regions under the MOS gate between the cell diffusions are connected by P^- diffusion to obtain a MOS-gate controlled low resistance path for turn-off. The IGTH was fabricated using a double-diffused DMOS process and 1200 V devices with controllable currents in excess of 150 A was obtained     

An investigation of the intrinsic delay (speed limit) in MTL/I2L

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of today's MTL/I²L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

Room-Temperature p-n-p AlGaAsSb–InGaAsSb Heterojunction Phototransistors With Cutoff Wavelength at 2.5 $mu$ m

Novel p-n-p AlGaAsSb-InGaAsSb heterojunction phototransistors (HPTs) grown by solid-source molecular beam epitaxy have been proposed and demonstrated. The p-n-p phototransistor structure provides a higher emitter injection ratio than its n-p-n counterpart, due to the large conduction band offset and almost continuous valence band edges between InGaAsSb and AlGaAsSb quaternary alloys. The resulting HPT devices exhibit high responsivities under a bias voltage above 0.3 V. A high room-temperature spectral responsivity of 2984 A/W is achieved at 2.24 mum, corresponding to an optical gain of 1652. The 50% cutoff wavelength of spectral photoresponse at room temperature is 2.50 mum. A room-temperature specific detectivity (D^*) of 8.3times10 ¹¹ cm middot Hz^1/2/W is obtained     

The effect of collector location on βuof I2L structures

I²L multicollector n-p-n transistor structures are used widely in LSI chips. Due to layout restrictions the collector could be at a distance from the injector. In this case, βuper collector is affected by the lateral voltage drop in the base. This effect becomes significant at higher current levels. In this work the lateral base region of the n-p-n transistor is modeled and a scheme is given to obtain the variation of βuwith the base current. The results are compared to measurements obtained using a three-collector structure.     

Characteristics of the emitter-switched thyristor

The first experimental demonstration of 600-V emitter-switched thyristors fabricated using an IGBT (insulated-gate bipolar transistor) process sequence is reported. The forward drop is less than that for the IGBT, but larger than that for a thyristor by about 0.5 V due to the thyristor current flowing via the MOSFET channel. A unique characteristic observed for these devices, not exhibited by any previous MOS-gated thyristor structures, is gate-controlled current saturation even after thyristor latch-up. Switching tests were performed up to a current density of 1000 A/cm² on single-unit cells and the measured turn-off times were about 7 μs     

The realization of a GaAs—Ge wide band gap emitter transistor

The fabrication and properties of an n-GaAs emitter, p-Ge base, n-Ge collector transistor which possesses significant current gain is described, These GaAs wide band gap emitter transistors have shown incremental current gains near 15 when operated at current densities up to 3500 A/cm². The doping level used in the base region was quite high (up to 5×10¹⁹/cm³in order to avoid a spurious Ge p-n junction in this region. The epitaxial deposition of the GaAs emitter region was carried out at a low temperature in order to also avoid a hidden p-n Ge junction. The low deposition temperature resulted in low (about 5×10¹⁵/cm³emitter doping levels. The general nature of the GaAs-Ge heterojunction energy-band diagram permits this high doping in the base or Ge region relative to the GaAs emitter region without reducing the current gain below unity. The observation of gain in this n-p-n heterojunction structure where the emitter is much more lightly doped than the base is considered to be confirmation of the theoretical proposals of Shockley and Kroemer.     

Lateral junction-isolated emitter switched thyristor

The operation of a 600-V junction-isolated lateral emitter switched thyristor (JI-LEST) is demonstrated. These devices exhibit an on-state voltage drop of 2.6 V at a current density of 100 A/cm² , a turn-off time of 20 μs, and a maximum controllable current density of about 200 A/cm²     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

Analysis of n-channel MOS-controlled thyristors

The turn-off of the n-channel MOS-controlled thyristor (NMCT) is analyzed using two-dimensional simulation. A lateral NMOS-controlled thyristor structure, LNMCT, suitable for HVIC application is also proposed. It is found that the operation of a parasitic lateral n-p-n transistor in NMCT-type structures degrades the forward voltage drop and the turn-off capability and hence should be suppressed. The maximum controllable current in the NMCT is not only a function of internal parameters, but also depends on external supply voltage. This indicates that snubberless operation of an MCT-type device is not feasible. The advantages and disadvantages of the NMCT are compared with those of conventional MCT structures. The LNMCT turn-off speed is limited by the large amount of holes existing in the substrate, resulting in a turn-off waveform similar to that of an LIGBT     

Epitaxially grown base transistor for high-speed operation

We developed a transistor with a very thin base to improve the speed of the intrinsic bipolar transistor. The epitaxially grown base transistor, or EBT, consists of an in-situ boron-doped epitaxial base layer that is photochemically grown, Photoepitaxy, with a low growth temperature of about 650°C, enables us to fabricate a very thin heavily doped layer. Our EBT has a base 65 nm thick and a peak boron concentration of 1 × 10¹⁹/cm³. Compared with high-speed bipolar transistors reported to date, EBT's have half the base width and ten times the peak boron concentration. The maximum current gain was about 500. Despite the very thin base, the Early voltage was about 70 V because of the high boron concentration. The EBT is potentially capable of very high-speed operation if combined with a structure that minimizes parasitic capacitance.     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors