Free charge transfer in charge-coupled devices

The free charge-transfer characteristics of charge-coupled devices (CCD's) are analyzed in terms of the charge motion due to thermal diffusion, self-induced drift, and fringing field drift. The charge-coupled structures considered have separations between the gates equal to the thickness of the channel oxide. The effect of each of the above mechanisms on charge transfer is first considered separately, and a new method is presented for the calculation of the self-induced field. Then the results of a computer simulation of the charge-transfer process that simultaneously considers all three charge-motion mechanisms is presented for three-phase CCD's with gate lengths of 4 and 10 µ. The analysis shows that while the majority of the charge is transferred by means of the self-induced drift that follows a hyperbolic time dependence, the last few percent of the charge decays exponentially under the influence of the fringing field drift or thermal diffusion, depending on the design of the structure. The analysis shows that in CCD's made on relatively high resistivity substrates, the transfer by fringing-field drift can be very fast, such that transfer efficiencies of 99.99 percent are expected at 5- to 10- MHz bit rates for 10-µ gate lengths and at up to 100 MHz for 4-µ gate lengths.     

Maximum free charge in two-phase surface charge-coupled devices

The maximum charge that can be stored and transferred efficiently in a surface CCD is significantly larger than in the buried channel device. However, whereas in the three-phase surface CCD the maximum charge depends primarily on clock voltage differences, in the two-phase device it depends on parameters which are fixed during fabrication. It is important therefore in the design of two-phase structures, to have a detailed understanding of how this charge depends on device parameters. The implanted barrier (IB) and stepped oxide (SO) structures are analysed by comparing the surface potentials obtained from one-dimensional models of the appropriate regions and a number of contrasting dependences found between the two types of CCD. A further limit to the maximum free charge for both devices is set when the field at the oxide-semi-conductor interface (and normal to it) approaches the breakdown field for Silicon. The presence of the implanted region in the IB. CCD gives rise to a radically different field limitation for the structure.     

Linearity of electrical charge injection into charge-coupled devices

This has been studied by measuring the generated higher harmonic components of a sinusoidal input. Results obtained with various injection methods and device geometries have been compared. Best results, with all harmonic components more than 40 dB below the fundamental, have been obtained for surface channel devices with a potential equilibration method in which the signal is applied to a second input gate, while the first input gate is held at a d.c. reference potential. It is concluded that this version of the potential equilibration method is readily adoptable for CCDs with any number of phases and that, if the active gate areas are suitably enlarged, harmonic distortions of less than -60 dB may be expected.     

Theoretical analysis of charge transfer in thin-film charge-coupled devices

The charge-transfer process in thin-film charge-coupled devices made from, e.g. hydrogenated amorphous silicon (a-Si:H) is analysed mathematically. This analysis considers the spatial coordinate in the transfer direction explicitly, while, by making use of the thin film feature, it is formulated as a quasi 1-D problem. In agreement with previous work, it is found that the thickness of the active layer influences the deleterious effect of localized states. However, it is shown that for a realistic distribution of localized states in undoped a-Si:H, the transfer inefficiency can approach the ultimate trap-free case when the active layer thickness is reduced to below 0.1 μm. Such a device can be operated at a frequency of slightly less than 100 kHz.     

Linearity of potential equilibration method of injecting charge into CCD's

The linearity of injecting charge into charge-coupled devices (CCD's) by potential equilibration method has been studied. Experimental results obtained agree Well with the theoretically derived expression for the input characteristic. If the two input gates have identical structures, i.e., the same oxide thicknesses and substrate dopings, input linearity is obtained irregardless to which gate the signal is applied. On the other hand, if the two gates are different, the signal should always be applied to the second gate in order to obtain a linear input function.     

Optimization of potential profiles in junction charge-coupled devices

Experimental results have shown that the junction charge-coupled device (JCCD) can compete with other types of CCD's in several applications, providing the channel potential can be made sufficiently smooth. Although devices have been fabricated with a charge-transfer intefficiency of 2 × 10^-s, the reproducibility was not satisfactory. Two new processes are described for fabricating JCCD's. By solving the two-dimensional Poisson equation numerically the parameters for the two processes are optimized. Computations for solving the lateral confinement problem of the JCCD have been made. A noncritical methtod is described to define the lateral boundaries of the channel. By simulating complete JCCD cells the influence of gate voltages and charge carriers in the channel was investigated. MOS effects caused by the aluminum interconnection layer on top of the devices also have been taken into account. The accuracy of the simulation method is demonstrated by comparing the results with both a one-dimensional simulation and another two-dimensional simulation which requires more computational effort. Based on the results of the computations JCCD's will be fabricated. Experiments will be carded out in order to verify the anticipated properties.     

Vertical charge transport and charge-handling capability injunction charge-coupled devices

In junction charge-coupled devices (JCCDs), the substrate p-n-p transistor can be applied as a versatile charge-sensing element for analog outputs, in digital circuits, and as a charge-normalizing device in optical line sensors. For all these applications, operation is controlled by clock voltage waveforms and properties of the JCCD. In particular the charge-handling capability is strongly related to vertical charge flow through the substrate p-n-p. This vertical charge transport is analyzed, showing that charge-handling capability can be defined only by taking into account vertical charge flow. Several experiments that confirm the predicted behavior is given. In addition, a method to speed up the normalization of charge packets in logic applications have been performed     

Linear charge injection to charge-coupled devices using capacitive metering

The input circuit of a charge-coupled device has the form of an m.o.s.f.e.t. Linear charge injection has been achieved by the negative feedback caused by a capacitor connected in series with the equivalent source electrode. The capacitor charge is reset between each sampling event. The distortion is similar to that obtained with fill-and-spill techniques, and the input voltage amplitude is more convenient.     

Numerical methods for the charge transfer analysis of charge-coupled devices

Charge transfer phenomenon in charge-coupled devices is characterized by a nonlinear partial differential equation of the parabolic type, usually coupled with a very undesirable nonlinear boundary condition. In this study, special treatment is made to the boundaries such that the nonlinearity of the boundary condition does not appear in the final calculation. Four possible finite-difference schemes for this problem are described and results compared. Through numerical experimentations, the linearized Crank-Nicolson scheme is proved to exhibit superior quality and is recommended for the exclusive use in studying the charge transfer phenomenon in CCD. Using this scheme, the charge transfer phenomenon of a two phase overlapping gate CCD has been studied and numerical results are presented. Special emphasis is directed toward the relative importance of the self-induced drift, fringing field drift and thermal diffusion currents. Also, the usefulness of approximating a spatial fringing field pattern by a constant value to the charge transfer phenomenon is discussed.     

Numerical studies of the charge capacity of surface-channel charge-coupled devices

The signal charge distribution and electrostatic potential of a three-phase charge-coupled device are found in a self-consistent manner. The length of the center gate is varied to simulate processing variations and their effect on charge capacity. Potential profiles are shown for a variety of charge levels and gate dimensions. The full-well charge capacity scales with the geometric gate length (down to at least 1 μm) in our example, although the partly filled charge level does not scale. A simple one-dimensional estimate of the full-well capacity is shown to be accurate.     

Computer model and charge transport studies in short gate charge-coupled devices

A computer model has been developed that simulates charge transport of carriers in a surface channel charge-coupled device. This model is based on the charge continuity and current transport equations with a time dependent surface field. The device structure of the model includes a source diffusion an input gate and transfer gate. The present model is the first real simulation of the input scheme of the surface-channel CCDs. The scooping and spilling techniques associated with the charge injection process are simulated by the input diffusion which is included in the model.As an application to a CCD practical problem the present model has been used to study the linearity of the electrical charge injection into surface channel charge-coupled devices. The generated harmonic components of a sinusoidal input are calculated using the transfer characteristics of the input stage obtained from the computer simulation.Using this model the spatial variations of the self-induced fringing field and total currents under the storage and transfer gates were computed. The charge transfer mechanisms for short-gate (L ≤ 8 μm) CCDs was investigated. It was found that for short gates the charge transfer efficiency is governed mainly by the fringing field and self-induced current mechanisms. The results of this study help to clarify the mechanism by which the signal-charge level and gate length affect the charge transfer efficiency.     

Experimental confirmation of an analytical model for charge transfer in charge-coupled devices

An analytical model for the charge loss as a function of transfer time under low charge levels in surface channel charge-coupled devices has been theoretically determined and experimentally confirmed. The model includes the effect of surface states. A new method of measuring charge transfer makes it possible to determine the role that surface states play in the degradation of signal charge transfer.     

The influence of interface states on incomplete charge transfer in overlapping gate charge-coupled devices

A simple and accurate model is used to estimate the incomplete charge transfer due to interface states trapping in the overlapping gate charge-coupled devices. It is concluded that trapping in the interface states under the edges of the gates parallel to the active channel limits the performance of the devices at moderate and low frequencies. The influence of the device parameters, dimensions, and clocking waveforms on the signal degradation is discussed. It is shown that increasing the clock voltages, reduces the incomplete charge transfer due to interface state trapping.     

Interlacing in charge-coupled imaging devices

Solid-state imaging devices to be used in commercial broadcast TV or the Picturephone® system have to supply the video information in a 2:1 interlaced timing format. An efficient way to achieve such a readout from charge-coupled area imaging devices of the frame transfer type is described. The resolution cells of the device are elongated in the vertical dimension to extend across the distance corresponding to two scanning lines in the display. For the two fields forming a full frame the charge generated by the incident light is integrated alternately underneath different sets of electrodes. Experimental results obtained on a 64 × 106 element frame transfer array are presented and compared to theory. They show that in a three-phase structure, by alternately integrating the charge underneath electrodes number 1 and numbers 2+3 jointly, the vertical resolution can be improved by about a factor of 2. This results in a limiting resolution in the vertical direction of about 75 percent of that given by the spatial pitch of the transfer cells. The value 75 percent is characteristic of all raster scanned imaging devices and is a result of the line scanned display. The usefulness of this scheme for line imaging devices is also discussed but is dismissed as being inferior to a bilinear approach with separate interdigitated integration sites.     

Noise measurements in charge-coupled devices

Measurements of the noise levels at the output of surface and bulk channel charge-coupled devices with three-phase overlapping polysilicon electrodes are presented. Pulser noise, correlated transfer noise, shot noise, dark current noise, and electrical insertion noise at the input have been measured and studied. The dependences of the electrical insertion noise and the transfer noise on charge packet size and clock frequency are discussed in detail and the latter related to interface state densities. New schemes and input circuits for low-noise electrical insertion of the signal charge are discussed. Our measurements indicate that the noise levels due to the intrinsic noise sources (transfer and storage noise) agree with our physical understanding of the device operation. The noise levels due to the extrinsic noise sources (pulser noise and electrical insertion noise) are above the expected theoretical values.     

Theory of amorphous-silicon charge-coupled devices

The theory of operation of amorphous-silicon charge-coupled devices has been studied numerically and analytically under the assumption that the localized states in amorphous-silicon are distributed exponentially with respect to energy. The transfer inefficiency ε is found to depend not only on the localized state density but also on the transit time and initial density of signal electrons. The approximate analysis shows thatln(epsilon)is a linear function of logarithmic clock frequency, and that its coefficient is given by the characteristic temperature which represents the steepness of the localized state density distribution in amorphous-silicon.     

Thermal carrier generation in charge-coupled devices

The build-up of thermally generated carriers in a charge-coupled device shift register is characterized by constructing a model for the generation inside a single shift-register bit. Using the model, theoretical response curves are constructed for two practical modes of operation where the contribution from the generation of carriers can be substantial. Experiments are presented which confirm all aspects of the theoretical response curves, including the presence of an initial period of reduced generation in one of the two modes. Procedures for determining generation parameters directly from observed CCD characteristics are presented and implemented. One generation parameter, the minority carrier lifetime τ, is determined by employing the CCD connected in a gate-controlled diode configuration; two others, the depleted surface generation velocity s0, and the general shape of the depletion layer, are determined utilizing a curve fitting procedure. The spatial variation in generation rates is also investigated and found to possess a distribution which is skewed positively and not Gaussian.     

Hot electrons in short-gate charge-coupled devices

Calculations are presented which show that the heating of electrons by high electric fields in short-gate surface-channel charge-coupled devices slows down the charge transfer process because of mobility reduction and hot carrier diffusion. Other consequences of carrier heating are a reduction of the interface-trapping noise and transfer inefficiency at short transfer cycles.     

Drift-aiding fringing fields in charge-coupled devices

Transverse electric fields at the Si-SiO/SUB 2/ interface (fringing fields) can aid transfer of charge from one potential well to another in charge- coupled devices (CCD). The magnitudes of these drift-aiding fringing fields are evaluated by an approximate analysis and also by computer. The analytical approach assumes zero space charge in the silicon and agrees with the computer solutions in that limit. When the depletion width becomes less than the gate width the fringing field is reduced considerably. Transit times associated with these fringing fields are evaluated. Trapping of charge in interface states rather than transfer of free charge is expected to be the fundamental limitation on speed and transfer efficiency in appropriately designed CCDs.