Error propagation analysis using FPGA-based SEU-fault injection

Error propagation analysis is one of the main objectives of fault injection experiments. This analysis helps designers to detect design mistakes and to provide effective mechanisms for fault tolerant systems. However, error propagation analysis requires that the chosen fault injection technique provides a high degree of observability (i.e., the ability to observe the internal values and events of a circuit after a fault is injected). Simulation-based fault injection provides a high observability adequate for error propagation analysis. However, the performance of the simulation-based technique is inadequate to handle today’s hardware complexity. As an alternative, FPGA-based fault injection can be used to accelerate the fault injection experiments, but the communication time needed for observing the circuit behavior from outside of the FPGA imposes severe limitations on the observability. In this paper, an observation technique for FPGA-based fault injection is proposed which significantly reduces the communication time as compared with previous scan-based observation techniques. Furthermore, this paper describes a SEU-fault injection technique based on a chain of parallel registers which reduces the time needed for injecting SEU faults as compared to the previous scan-based fault-injection techniques. As a case study, a 32-bit pipelined processor has been used in the fault injection experiments. The experimental results show that when a high degree of observability is required (e.g., error propagation analysis), the proposed fault injection technique is over 1166 times faster than simulation-based fault injection, whereas the traditional scan-based technique can achieve only a speedup of about 2–3 – which means that the proposed technique is about 500 times faster than the traditional scan-based technique. Such results are supported by theoretical performance analysis. This speed increase has been achieved without excessive increase in FPGA resource overhead, for example, the FPGA overhead of the proposed technique is only 2  3% higher than that of the traditional scan-based technique.     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.     

Emulation-based fault analysis on RFID tags for robustness and security evaluation

This paper presents an FPGA (field-programmable gate array) based fault emulation system for analysis of fault impact on security and robustness of RFID (radio frequency identification) tags. This emulation system that deals with any RFID protocol consists of two tag-reader pairs, a fault injection module and an emulation controller all implemented in a single FPGA. The designed approach performs single event upset (SEU) and single event transient (SET) fault injection and permits with high flexibility to set communication scenarios and related parameters. Moreover, we propose a classification of produced errors to evaluate fault impacts and identify most sensitive tag flip-flops causing large number of failures and security concerns. The proposed fault injection approach provides suitable means to increase tags' security and robustness. In our experimentation campaign, an ultra-high frequency (UHF) tag architecture has been exposed to intensive SEU and SET fault injections. The duration of the campaign including results analysis is 30 min in where 6,215,316 faults are experimented. Our results have shown that the tag has tolerated 61.82% of SEUs and 67.83% of SETs. The flip-flops that constitute the tag FSM (finite state machine) have been identified as the most sensitive parts causing large number of failures.     

具有自律特征的网络故障管理框架

自律计算是IT研究的一个热点，它旨在设计出一种具有自我配置、自我优化、自我恢复和自我保护的计算机系统，使系统能够根据管理员给定的高层次目标进行自我管理。文章根据基本的控制理论．结合IBM提出的自律计算模型，将基于反馈的反应式控制和基于前馈的预测式控制相结合，运用于网络故障管理系统中，提出了一个具有自律特征的网络故障管理框架。最后，根据该故障管理系统的实现经验，分析了框架实现中的关键技术。     

Fast and accurate FPGA-based framework for processor architecture vulnerability analysis

This paper presents a fast, accurate, and flexible FPGA-based fault emulation platform, namely FARAVAM that can be exploited for AVF analysis in modern microprocessors. The proposed approach provides fault injection capabilities supporting automatic modification of post-synthesis net-lists and introduces a highly controllable and observable transient fault analysis environment. The presented vulnerability analysis platform using both exhaustive and random fault emulation approaches, provides useful information for identifying areas threatening reliability to make processors more fault tolerant. We applied our platform for extracting the best trade-offs between precision and speed up in vulnerability analysis of MIPS processor. The experimental results indicate that in addition to having high precision we obtain about seven orders of magnitude speed up in comparison with simulation based vulnerability analysis techniques.     

A New Approach to Software-Implemented Fault Tolerance

A new approach for providing fault detection and correction capabilities by using software techniques only is described. The approach is suitable for developing safety-critical applications exploiting unhardened commercial-off-the-shelf processor-based architectures. Data and code duplications are exploited to detect and correct transient faults affecting the processor data segment, while control flow instruction duplication is used for detecting and correcting faults affecting the code segment. Results coming from extensive fault injection campaigns showed the effectiveness and the limitations of the method.     

Using multi-stage and stratified sampling for inferringfault-coverage probabilities

Development of fault-tolerant computing systems requires accurate reliability modeling. Analytic, simulation, and hybrid models are commonly used for obtaining reliability measures. These measures are functions of component failure rates and fault-coverage (probabilities). Coverage provides information about the fault and error detection, isolation, and system recovery capabilities. This parameter can be derived by physical or simulated fault injection. Statistical inference has been used to extract meaningful information from sample observation. The problem of conducting fault injection experiments and statistically inferring the coverage from the information gathered in those experiments is addressed in this paper. We perform statistical experiments in a multi-dimensional space of events. In this way all major factors which influence the coverage (fault locations, timing characteristics of the fault, and the workload) are accounted for. Multi-stage, stratified, and combined multi-stage and stratified sampling are used in this paper for deriving the coverage. Equations of the mean, variance, and confidence interval of the coverage are provided. The statistical error produced by the injected faults which do not induce errors in the tested system (also known as the nonresponse problem) is considered, A program which emulates a typical fault environment was developed and four hypothetical systems are analyzed     

Simulated Fault Injection Using Simulator Modification Technique

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog‐based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault‐tolerance mechanisms.     

Strategies of fault tolerant operation for three-level PWM inverters

This paper proposes fault tolerant operation strategies for three-level neutral point clamped pulsewidth modulation inverters in high power, safety-critical applications. Likely faults are identified and fault tolerant schemes based on the inherent redundancy of voltage vectors are presented. Simulation verification is performed to show fault handling capabilities. Prototyping and principle investigation are performed on a 150-KW inverter and testing results are presented.     

Path-Based Error Coverage Prediction

We present an analytical technique that uses fault injection data for estimating the coverage of concurrent error detection mechanisms in microprocessors. A major problem in such estimations is that the coverage depends on the program executed by the microprocessor as well as the input sequence to the program. We propose a method that predicts the error coverage for a specified input sequence based on fault injection data obtained for another input sequence. Our results show that post-injection analysis is a promising approach for reducing the cost of coverage estimation.     

基于JTAG的硬件故障注入工具

可靠性是评价容错计算机的重要性能指标之一,评价系统的可靠性在计算机系统的设计及实现阶段都有重要意义,故障注入法是可靠性评测的一种常用方法。在通用的JTAG调试技术基础上,描述了一种针对CPU的硬件故障工具,并通过仿真实验进行了验证。该硬件注入工具基于IEEE标准,只要知道目标芯片的边界扫描链,就可以进行故障注入工作;同时,该工具对目标系统的故障注入工作由硬件完成,对操作系统透明,可以有效地突破操作系统的保护机制。     

Switched-capacitor high-speed emulator for real-time fault location in electrical power systems

This research presents a discrete-time transmission line model based on the propagation of travelling waves. In this approach, the transmission line is emulated by means of many interconnected unit delay cells implemented with switched-capacitor (SC) circuits. The accuracy and limitations of this method is compared to existing transconductance–capacitor solutions and is evaluated in the frame of a novel power network fault location method based on the electromagnetic time-reversal principle. The impact of the non-ideal effects associated to analog CMOS SC circuits, such as amplifier finite gain, offset and switch charge injection is evaluated in the same context. A possible application of the model for the simulation of interconnected or multi-conductor lines is also discussed. After an AMS 0.35 µm process implementation, it is shown that the present method allows a fault location within 1% resolution and is a hundred times faster than nowadays digital solutions. This speed improvement allows a fault location within 160 ms, making thus real-time applications realistic.     

Dynamic control and performance of a unified power flow controller for stabilizing an AC transmission system

This paper presents dynamic control and performance of a unified power flow controller (UPFC) intended for installation on a transmission system consisting of two sets of three-phase transmission lines in parallel. When no UPFC is installed, interruption of either three-phase line due to a fault reduces an active power flow to half, because the line impedance becomes double before the interruption. Installing the UPFC makes it possible to control an amount of active power flowing through the transmission system. The validity of the theoretical analysis developed in this paper is verified by experiments using a 10-kVA laboratory setup, as well as a computer simulation.     

Assignment of Dynamically Perceived Tasks by Token Passing in Multirobot Systems

The problem of assigning tasks to a group of robots acting in a dynamic environment is a fundamental issue for a multirobot system (MRS) and several techniques have been studied to address this problem. Such techniques usually rely on the assumption that tasks to be assigned are inserted into the system in a coherent fashion. In this work we consider a scenario where tasks to be accomplished are perceived by the robots during mission execution. This issue has a significative impact on the task allocation process and, at the same time, makes it strictly dependent on perception capabilities of robots. More specifically, we present an asynchronous distributed mechanism based on Token Passing for allocating tasks in a team of robots. We tested and evaluated our approach by means of experiments both in a simulated environment and with real robots; our scenario comprises a set of robots that must cooperatively collect a set of objects scattered in the working environment. Each object collection task requires the cooperation of two robots. The experiments in the simulation environment allowed us to extract quantitative data from several missions and in different operative conditions and to characterize in a statistical way the results of our approach, especially when the team size increases.     

Real Time Fault Diagnosis with Tests of Uncertain Quality for Multimode Systems and its Application in a Satellite Power System

Dynamic fault diagnosis must consider complex fault situations such as fault evolution, coupling, unreliable tests and so on. Previous dynamic fault diagnostic models and inference algorithms are mainly designed for the steady state systems, which are not suitable for the multimode systems. In this paper, a time varying dynamic model to solve the multimode fault diagnosis problem is proposed. Its structure and formulation are presented. Fault diagnosis based on this model is realized by means of inference calculation given the test result, which is formulated as an optimization problem. A new algorithm to solve this problem is proposed. Simulation experiments on different scenarios are carried out to validate the model and the algorithm. As an example, the case of a satellite electrical power system is studied in detail. Both the simulation result and the application result show that the method proposed in this paper can be used to solve the dynamic fault diagnosis problem for multimode systems considering the complex circumstances such as uncertain tests and system delay.     

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.     

一种基于OFDMA系统的频率复用方法

频率复用作为提高小区边缘用户性能的有效方式已被广为研究。然而,如何在提高小区边缘用户性能的同时,使频谱利用率得到有效提高仍是一个有待解决的问题。在以正交频分多址(OFDMA)为基本多址方式的第4代(4G)系统中该问题尤为突出。为此,该文提出了一种OFDMA系统中的频率复用方法,通过抑制小区间干扰提高小区边缘用户性能;同时,根据小区中心与小区边缘通信环境的差异,分别对其实施不同的频率复用策略使频率复用系数接近于1以提高频谱利用率。仿真结果表明,与未经过频率规划的全频率复用相比,该文提出的频率复用方法提高了系统吞吐量并显著改善了小区边缘用户性能。     

FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC

Recently, system-on-chips (SoCs) are increasingly employed in reliable applications for their high-performance and high-densities. Moreover, the structure shrinking of SoC leads to its proneness to radiation-induced soft errors. This paper presents a fine-grained fault injection framework for SoC (FFI4SoC) to assess the reliability of SoC against soft errors. FFI4SoC facilitates fault injection for SoC by defining the primary components and rules that are required by fine-grained fault injection. Furthermore, based on FFI4SoC, we develop a fine-grained fault injection tool named SSIFFI for bare-metal MicroZed. The design of SSIFFI is presented in order to illustrate the application of FFI4SoC. Finally, SSIFFI is engaged in simulated fault injection experiments to explore the cause of single event functional interrupts (SEFIs) and to validate functional properties of FFI4SoC. The experimental results disclose detailed reasons for SEFI and prove that FFI4SoC can be employed to assess reliability of SoC well with the merit of fine-grained injection.