共查询到20条相似文献,搜索用时 31 毫秒
1.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
2.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献
3.
The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V GS⩽5 V and B DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μp (hole mobility) of RONO p-channel devices. At 300 K, μp(RONO) is 14-8% smaller than μp(SiO2) over the entire range of gate biases, while μn(RONO) (electron mobility of n-channel RONO devices) is also smaller than μn(SiO2) and reaches only 96% of μn(SiO2) at V GS=5 V. At 100 K, μn(RONO)/μn (SiO2) at V GS=5 V is increased to 1.10, however, μp(RONO)/μp(SiO2) at V GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO2 inverters 相似文献
4.
A simplified analytical expression for the temperature dependent saturated I D-V D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I D versus V G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I D and more severe gate voltage hysteresis characteristics 相似文献
5.
Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 μm, and a family of characteristic plots of substrate current, normalized to drain current, I SUB/I D, rather than (V DS-V DSAT)-1 was obtained. For channel lengths greater than 0.5 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the characteristics are independent of channel length. For channel lengths in the range of 0.15 μm, the normalized substrate current at constant V DS increases with decreasing channel length. However, as the channel length is decreased below 0.15 μm, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both 相似文献
6.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
7.
Vuillaume D. Marchetaux J.-C. Lippens P.-E. Bravaix A. Boudou A. 《Electron Devices, IEEE Transactions on》1993,40(4):773-781
The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V d/8 to V d) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I d-V g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-V g degradation 相似文献
8.
The tradeoff between common-emitter current gain (β) and Early voltage (V A) in heterojunction bipolar transistors (HBTs) where the bandgap varies across the base has been studied. The Early voltage depends exponentially on the difference between the bandgap at the collector side of the base and the largest bandgap in the base, allowing very high Early voltages with only very thin narrow bandgap regions. Using Si/Si1-xGex/Si HBTs with a two-layer stepped base, βV A products of over 100000 V have been achieved for devices with a cutoff frequency expected to be about 30 GHz 相似文献
9.
The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field 相似文献
10.
Hida H. Tsukada Y. Ogawa Y. Toyoshima H. Fujii M. Shibahara K. Kohno M. Nozaki T. 《Electron Devices, IEEE Transactions on》1989,36(10):2223-2230
The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5-μm gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average V t of 0.18 (-0.46) V, a V t standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450 (300) mS/mm. The V t shift is less than 50 mV with a decrease in gate length down to 0.5 μm. The gate forward turn-on voltage V f is more than 0.9 V, i.e. about 1.6 times that for MESFETs. This superiority in V f, preserved in the high-temperature range, leads to an improvement in noise margin tolerance by a factor of three. In addition, 31-stage ring oscillators operate with a power consumption of 20 (1.0) mW/gate and a propagation delay of 4.8 (14.5) ps/gate. Circuit simulation based on the experimental data predicts 140 ps/gate and 1 mW/gate for DMT direct-coupled FET logic circuits under standard loading conditions. DMTs and the technology developed here are very attractive for realizing low-power and/or high speed LSIs 相似文献
11.
A metal-base transistor of the MOMOM type with large current gain is reported. It uses Bi(Ba,Rb)O3 and oxide semiconductors. I -V curves for a Bi(Ba,Rb)O3 base transistor in the common-base configuration were studied from room temperature to 30 K. Current gain α~1 was obtained at 50 K. Transport behavior is determined by analysis of threshold voltages and derivatives dI c/dV cb 相似文献
12.
An analytical expression for the recombination current in a forward-biased p-n junction is derived and it is shown that formulas given for the recombination current in most textbooks overestimate the recombination current by a large factor of the order of (V bi-V )/V th where V bi is the built-in voltage, V is the applied forward-bias voltage, and V th is the thermal voltage 相似文献
13.
The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I -V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V 0=0.27 V , V 1=0.42 V, and V 2=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V 0=0.35 V, V 1=0.42 V, V 2=0.54 V, and V 3=0.59 V. A suggestion of an integrated device structure using this concept is also presented 相似文献
14.
CW measurement of HBT thermal resistance 总被引:2,自引:0,他引:2
Measurements of the temperature dependence of β and V BE were made on AlGaAs-GaAs HBTs and used to determine device thermal resistance. The measurements were CW and not switched or pulsed in order to have a simpler procedure. With base doping greater than 1019 cm-3, HBTs have negligible base-width modulation (i.e., flat I C versus V CE characteristics) which makes CW thermal resistance measurement especially direct and simple 相似文献
15.
Ng G.I. Pavlidis D. Tutt M. Weiss R.M. Marsh P. 《Electron Devices, IEEE Transactions on》1992,39(3):523-532
Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In0.52Al0.48As/InxGa1-x As(0.53<x <0.70) HEMTs. The input-noise voltage spectra density is insensitive to V DS bias and shows a minimum at V GS corresponding to the peak g m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V DS bias 相似文献
16.
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I g-V g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I g- V g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I g-V g measurements 相似文献
17.
The looping effect in the I D-V D (drain-current-drain-voltage) characteristics of GaAs MESFETs on semi-insulating substrates has been studied using a two-dimensional numerical analysis. Both the transient and the steady-state behaviors of the looping phenomenon were simulated. Peak voltage- and frequency-dependent behaviors of the looping effect are analyzed. The I D-V D loop is due to the difference in the distribution of ionized EL2 concentration when the drain voltage rises and falls because of the trapping process of EL2s. The output conductance is also found to be frequency-dependent and is explained by the frequency-dependent modulation of the potential barrier height at the channel/substrate interface due to the drain-voltage variation 相似文献
18.
Nakagome Y. Itoh K. Takeuchi K. Kume E. Tanaka H. Isoda M. Musha T. Kaga T. Kisu T. Nishida T. Kawamoto Y. Aoki M. 《Solid-State Circuits, IEEE Journal of》1991,26(7):1003-1010
Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs 相似文献
19.
Seung-Moon Yoo Ejaz Haq Seung-Hoon Lee Yun-Ho Choi Soo-In Cho Nam-Soo Kang Daeje Chin 《Solid-State Circuits, IEEE Journal of》1993,28(4):499-503
Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V CC level; (2) compensation of DC generators, V BB and V PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation 相似文献
20.
Scherrer D. Kruse J. Laskar J. Feng M. Wada M. Takano C. Kasahara J. 《Electron Device Letters, IEEE》1993,14(9):428-430
The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V th=0.3 V achieved a maximum DC transconductance of g m=489 mS/mm at V ds=1.5 V and I ds=18 mA. Operating at 0.5 mW of power with V ds=0.5 V and I ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F min=1.2 dB and the average associated gain was G a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications 相似文献