Random telegraph signal: A sensitive and nondestructive tool for gate oxide single trap characterization

This paper presents the electrical characterization of thick and thin SiO₂ oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.     

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N₂O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N₂O nitridation piles up in the oxide at the Si–SiO₂ interface regardless of nitridation time. The results obtained show improved breakdown field (E_bd), and charge-to-breakdown (Q_bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density (D_it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.     

Carrier trapping in thin N2O-grown oxynitride/oxide di-layer for PowerMOSFET devices

A detailed study of the carrier trapping properties shown by the silicon/oxynitride/oxide gate layers in PowerVDMOS technologies is reported. A quantitative analysis of hole and electron trap densities versus the specific N₂O based nitridation process, extracted from Fowler–Nordheim constant current stress kinetics, allows a deep understanding of the role played by those defects in the susceptibility of every nitrided layer.     

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF₂ is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements

We have investigated gate and drain current noise on strained-channel n-MOSFETs with a SiGe virtual substrate and a 12 Å thermally nitrided gate oxide using low frequency noise measurements. The power spectral densities (PSD) of the flat-band voltage fluctuations are extracted from both gate and drain current noise. We show that the same oxide trap density profile is involved in drain and gate low frequency noise. A comparison with standard n-MOSFET transistors with the same gate stack process is presented. The flat-band voltage PSD concept is also used to compare both technologies to show that bulk and dielectric quality of strained devices are not degraded with regard to standard n-MOSFETs.     

Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

ISSG及其氮化工艺对NBTI效应的改善

本文在对ISSG工艺特性简单分析的基础上讨论了ISSG氧化物薄膜的可靠性问题。讨论了ISSG工艺及其相关的氮化工艺对NBTI的改善原理。数据表明ISSG工艺及其相关的氮化工艺对NBTI效应有明显的改善作用。由于原子氧的强氧化作用,ISSG工艺中最终得到的氧化物薄膜体内缺陷少,界面态密度也比较小,氧化物薄膜的质量比较高。ISSG氮化工艺与传统炉管氧化物薄膜的氮化工艺的主要区别在于N所集中的位置不一样。ISSG工艺氮化是把等离子态的N^＋注入到多晶硅栅和SiQ2的界面,不会增加SiQ2和Si衬底的界面态,从而可以显著改善NBTI效应。而传统炉管氧化物薄膜的氮化是用NO或者N2O把N注入到SiQ2和Si衬底的界面,这样SiQ2和Si的界面态就会增加,从而增强NBTI效应。     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Theory and experiments on surface 1/f noise

A theoretical low-frequency noise model for the epitaxial-channel surface field-effect structure is presented where random modulation of the channel conductance arises from fluctuation of charges trapped at the oxide trap states near the Si-SiO2interface. In this model, charge fluctuation in the oxide traps arises from carrier tunneling between the fast interface surface states and the oxide trap states. A second fluctuation, at higher frequencies, arises from the random thermal emission and capture of electrons and holes at the fast interface states through the thermal or Shockley-Read-Hall process. Different oxide trap densities were introduced into the interface region of the metal-oxide-silicon field-effect structures using a carefully controlled and reproducible oxygen heat treatment technique. Energy distributions of the oxide trap densities are obtained from capacitance measurements. Humps are observed between the flat band and the onset of strong surface inversion (lower half of the bandgap) in both the noise power and the oxide trap density versus gate voltage (or surface band bending) plots. Theoretical noise power calculations using the experimental oxide trap density profile from the capacitance-voltage data agree very well with the experimental noise humps in both magnitudes and fine structures. It is shown that the frequency spectra of noise depend strongly on the oxide trap density profile in the oxide. It is suggested that the oxide traps are due to the excess oxygen at the SiO2-Si interface.     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Oxide thickness dependence of nitridation effects on TDDB characteristics

Wet oxide thicknesses dependence of nitridation effects on electrical characteristics, charge trapping properties and TDDB (Time Dependent Dielectric Breakdown) characteristics have been investigated. It is found that the difference of conduction current between the wet and nitrided wet oxide increases with increasing oxide thickness both for negative and positive bias to the gate until constant current stress is applied. After the stress, with decreasing oxide thickness both in wet and nitrided wet oxide leakage current increases. Up to 60 Å no difference was observed between the wet and nitrided wet oxide but at 50 Å nitrided wet oxide has less increase of current comparing to the wet oxide for the same stress. In wet oxide with increasing stress current density initial hole trap decreases but electron trap increases whereas in nitrided wet oxide has less initial hole trap and also electron trap is less comparing to the wet oxide. Both in wet and nitrided wet oxide for negative bias stress, time to 50 % breakdown decreases with decreasing thickness but at 50 Å a turn-around effect was observed due to nitridation i.e., the 50 % breakdown time is greater for nitrided wet oxide comparing to the wet oxide. On the contrary, for positive bias stress 50 % breakdown time increases with decreasing oxide thickness both in wet and nitrided wet oxide. For positive bias also a turn-around effect is observed at 50 Å i.e., 50% breakdown time is less in nitrided wet oxide comparing to the wet oxide. The improved reliability of nitrided wet oxide at the thin region of 50 Å seems to be due to the increase of more Si---N bond to the interface of oxide and Si comparing to the thick oxide of above 60 Å for the same nitridation conditions.     

Identification of electron trap location degrading low-frequency noise and PBTI in poly-Si/HfO2/interface-layer gate-stack MOSFETs

Identification of electron trap location in HfO₂/interface-layer (IFL) of poly-Si/TiN/HfO₂/SiO₂ gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.     

Correlation between most 1/f noise and CCD transfer inefficiency

The 1/f noise in MOS transistors has been investigated and is shown to correlate with charge transfer inefficiency experiments on surface-channel CCDs. Both independent phenomena can be quantitatively explained by the same interface state model. The oxide trap density turns out to vary by more than a factor 10. The 1/f noise is compared with McWhorter's number fluctuation model and with the mobility fluctuation model. The oxide trap density is calculated from the charge transfer inefficiency in surface CCDs. Both the quantitative agreement between oxide trap density and 1/f noise and the observed dependence of 1/f noise on gate voltage here give strong arguments in favour of the McWhorter model. The investigated MOS transistors fall into a category that cannot be explained by the present mobility fluctuation model.     

Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications

For the first time, the feasibility of ultrathin oxides grown by high pressure oxidation (HIPOX) technology in O₂ ambient and nitrided in N₂O ambient with rapid thermal processing has been investigated in order for them to be used as a gate oxide of ULSI devices. The dielectric breakdown electric field (E _BR) and the midgap interface trap density (D _itm) of the nitrided-HIPOX oxide are ?13:9MVcm^?1 and 2 × 10¹⁰cm^?2eV^?1 respectively which are almost the same as those of the control oxide and the nitrided-control oxide. The time-tobreakdown (t_BD) of the nitrided-HIPOX oxide is longer than that of the control oxide at low electric field (<10^?4 A cm^?2) owing to the combination of nitrogen and defects near the Si?SiO₂ interface during nitridation. The lifetimes of the nitrided-HIPOX oxides increase initially, reaching a maximum value of 1:2 × 10⁹ s at a stress current density of 1 × 10^?6 A cm^?2,corresponding to over 10 years, and then decrease as nitridation proceeds.     

Reduction of the anomalous VT behavior in MOSFETs with high-κ/metal gate stacks

This study investigates the impact of different nitridation processes on hafnium silicon oxynitride (HfSiON) dielectrics. It is demonstrated that the threshold voltage (V_T vs. L_g) behavior at short gate lengths is strongly impacted by the nitridation process, depending on the Hf/(Hf+Si) ratio and the HfSiON thickness. A Plasma nitridation in oxidizing ambient results in a modification of the dielectric that can explain the anomalous V_T behavior in devices integrated with hafnium-based dielectrics and metal gate. Reduction in anomalous V_T behavior and limited gate leakage is achieved by applying a thermal nitridation in a NH₃ ambient on Hf-rich silicon oxynitride.