Sulfide treated GaAs MISFET's with gate insulator of photo-CVDgrown P3N5 film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P₃N₅ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s ~1.0×10⁴ s, due to excellent properties of sulfide treated P₃N₅/GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm²/V·sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P₃N₅/GaAs interfacial properties, GaAs-MIS diodes are also fabricated     

InP MISFET's with Al2O3/Native Oxide double-layer gate insulators

Enhancement-mode InP MISFET's with anodic Al2O3/ native oxide double-layer for gate insulator are fabricated by anodization processes in electrolyte and in oxygen plasma. Such gate structure greatly improves the device performance; high effective electron mobilities of 1500-3000 cm²/V . s and marked reduction of drain current instability were simultaneously achieved. This device performance is consistent with the interface properties obtained by C-V measurements. InP MISFET inverters as well as ring oscillators are also fabricated to demonstrate the stability of the circuit at low frequency and to show the capability of the process employed.     

InP MISFET's with plasma anodic Al2O3and interlayed native Oxide gate insulators

InP MISFET's, with native oxide film interlayed between plasma anodic Al2O3film and the InP substrate, has been fabricated and showed the instability of the drain current reduced less than ± 4 percent for the period of 5 µs ∼ 5 × 10⁴s. The effective electron mobility is 2100 ∼ 2600 cm²/V.s at room temperature. The CV characteristics of MIS diodes and AES in-depth profiles are also discussed with respect to effects of interlaying native oxide film on device characteristics.     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

Undoped InP/InGaAs heterostructure insulated-gate FET's grown byOMVPE with PECVD-deposited SiO2 as gate insulator

The fabrication and performance of InP/InGaAs insulated-gate FETs which use a heterojunction to isolate the channel electrons from the semiconductor-insulator interface are discussed. Plasma-enhanced chemical vapor deposition (PECVD) was used to deposit SiO₂ on InP to form the gate insulator. Since the device structure is undoped, channel electrons are accumulated by the gate-induced field across the insulator. Extrinsic transconductances of 130 mS/mm (300 K) and 210 mS/mm (77 K) were achieved for 1.5- μm gate-length devices. Gate-drain breakdown voltages in excess of 20 V were also measured     

Thin fluorinated gate dielectrics grown by rapid thermal processingin O2 with diluted NF3

The authors report the application of rapid thermal processing (RTP) to the fabrication of ultrathin (~10 nm) high-quality fluorinated oxides in O₂+NF₃ (100 ppm diluted in N₂). NF₃ was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O₂ during the initial stage of RTO. The oxidation rate was enhanced because of the presence of NF₃. In addition, F depth profiles in fluorinated oxides were dependent upon the process conditions. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. The initial interface state density (D_t) was found to decrease with F incorporation. The results suggest that the interfacial F incorporation plays a major role in determining the interface hardness for both hot-electron and radiation damages     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

CaF2 surface passivation of lead selenide grown on BaF2

A new method of surface passivation of PbSe epitaxial layers by growing a thin epitaxial CaF₂ layer is proposed. Improvement in photoluminescence (PL) intensity is observed when the PbSe layer is passivated. The minority carrier lifetime (τ), measured by photo-current decay method corroborates PL measurements and shows a consistent, albeit not considerable, improvement in the lifetime of PbSe samples after surface passivation. The positive effect of surface passivation, especially at low heat-sink temperature, offered by a new passivating material is critically important for IV-VI material-based infrared detector and sensor applications.     

MOS characteristics of fluorinated gate dielectrics grown by rapidthermal processing in O2 with diluted NF3

Rapid thermal processing (RTP) was applied to the fabrication of the ultrathin (~10 nm) high-quality fluorinated oxides in O₂+NF₃. NF₃ (diluted in N₂) was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O₂ during the initial stage of RTO. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. It was found that SiO₂ with a small amount of F incorporated shows reduced interface state generation under F-N injection, whereas excessive F incorporation is detrimental     

p-Channel TFT's using magnetron-sputtered Ta2O5films as gate insulators

Metal-gate thin-film transistors (TFT's) have been fabricated in layers of laser-recrystallized polycrystalline silicon on fused quartz substrates at processing temperatures below 625°C. Tantalum pentoxide (Ta2O5) was used as a gate insulator instead of a conventional thermally grown silicon dioxide (SiO2). Ta2O5gate insulator was deposited onto the recrystallized silicon layer at room temperature, using an RF-magnetron sputtering system. The reactive ion etching method, using CF4as a reactive gas, was employed in patterning deposited Ta2O5. These TFT's have exhibited p-channel depletion-mode characteristics with a threshold voltage of 2.5 V and a transconductance of 70 µS at Vg= - 2 V. An on-off current ratio exceeding 10⁵has been obtained.     

Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

Effects of the base layer in Si₃N₄/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si₃N₄ film property in Si₃N₄/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si₃N₄ stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si₃N₄/SiON stack dielectrics and the strained layer thickness near SiON/Si interface.     

Direct bonding between InP and rare earth iron garnet grown on Gd3Ga5O12 substrate by liquid phaseepitaxy

The bonding of InP and rare earth iron garnet grown on Gd₃ Ga₅O₁₂ substrate without any additional material demonstrated. After chemical treatment, heat treatment in H₂ ambient results in the bonding of the samples. This process is applicable to the integration of semiconductor and magneto-optic devices     

SiO2 masking against phosphorus diffusion using a P2O5 source

The masking of silicon against deep P₂O₅ diffusion by a 1-μ thick SiO₂ layer has been investigated. One aspect of masking failure has been related to mounds of phosphorus silicate glass, grown on the oxide during the P₂O₅ deposition, causing spot penetration of phosphorus through the oxide and into the silicon. Such spots can increase in density, diameter and depth during the subsequent diffusion. They link up and form a continuous, but not uniform n-type layer under the oxide. Residual water vapour in the deposition systems and particle deposits on wafers during washing have been shown to be the factors that contribute to the growth of mounds.     

InP/InGaAs HBTs with n+-InP contacting layers grown byMOMBE using SiBr4

InP/InGaAs heterojunction bipolar transistors (HBTs) with low resistance, nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers have been demonstrated with excellent DC characteristics. A specific contact resistance of 5.42×10^-8 Ω·cm², which, to the best of our knowledge, is the lowest reported for TiPtAu on n-InP, has been measured on InP doped n=6.0×10¹⁹ cm^-3 using SiBr₄. This low contact resistance makes TiPtAu contacts on n-InP viable for InP/InGaAs HBTs     

Ho~(3+)离子及HoP_5O_(14)晶体的光谱性质

根据HoP_5O_(14)的吸收光谱和荧光光谱,用Judd-Ofelt理论计算了Ho~(3+)的强度参数.并计算了激发能级的辐射跃迁速率、辐射寿命、荧光分支比和积分发射截面等光谱参数.     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Walk-out phenomena in 6H-SiC mesa diodes with SiO2/Si3N4 passivation and charge trapping in dry and wet oxides on N-type 6H-SiC

The drift or “walk-out” of the breakdown voltage in 6H-SiC mesa diodes passivated by a double layer of 1000 Å SiO₂ and 3000 Å Si₃N₄ was studied and related to the charge trapping in the oxide. The first-order trapping kinetics using four distinct electron traps with trapping cross-sections in the range 10⁻¹⁶ to 10⁻¹⁹ cm² were found to best describe the breakdown voltage drift curves. The wet oxide trapping cross-sections are 2 to 10 times larger compared to the dry oxide ones, resulting in about one order of magnitude faster charging of the traps. No significant differences in the amount of drift and saturation level of breakdown voltage were found between the different passivations. The influence of UV illumination, supplied by a HeCd laser with wavelength 325 nm, on the walk-out characteristics and on the reverse current was also investigated. The build-up of the surface states was observed in wet oxide under UV illumination and DC stress. The results are consistent with the coexistence of large concentrations of positive charge and acceptor type deep interface electron traps. The walk-out is a result of the acceptor states being filled by hot electrons supplied by the mechanism of avalanche injection. The suitability of the walk-out measurements as a tool for characterisation of the charge trapping properties of the passivation is demonstrated.     

激光合成非晶态Si3N4粉末

本文描述了大功率CO2激光辐照SiH4+NH3的快速流动气体合成Si3H4超细粉末的实验,揭示了激光谱线变化对合成反应的影响。讨论了粉末红外吸收光谱的畸变现象等。     

Low threshold current GaAs/AlGaAs GRIN-SCH lasers grown bymolecular beam epitaxy on Si3N4 masked substrates

High-performance single-quantum-well graded-refractive index separate confinement heterostructure (SQW GRINSCH) laser have been grown by molecular beam epitaxy on Si₃N₄ patterned GaAs (100) substrates. Lasers grown on stripe windows orientated in the [011] direction have optical waveguiding and current confinement supplied by facetting occurring during growth. Lasers fabricated on 10 μm wide Si ₃N₄ openings have threshold currents as low as 15 mA for a 500 μm-long cavity. The current density required to reach optical transparency is 144 A/cm²; an internal quantum efficiency of 81%, and a peak optical power of 70 mW per facet has been obtained. Device performance comparable to ridge lasers is observed in a self-aligned laser process     

InAs0.97N0.03/InGaAs/InP multiple quantumwell lasers with emission wavelength λ=2.38 μm

Application of a novel InAsN alloy on a laser device is reported for the first time. The four-period InAs_0.97N_0.03-In_0.53Ga_0.47 As-InP strained multiple quantum well laser, grown by gas source molecular beam epitaxy with an RF-coupled plasma nitrogen source, lased under pulsed operation at 2.38 μm at 260 K. A threshold current density of 3.6 KA/cm² at 260 K and a characteristic temperature of 62 K have been achieved