Small-signal gate-to-drain capacitance of MOSFET as a diagnostic tool for hot-carrier induced degradation

In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap.     

Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C_gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET’s has been reviewed and demonstrated. By analyzing the change in C_gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I_bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q_ot, through gate-to-substrate capacitance (C_gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device’s structure.     

Characterization of charge trapping in submicrometer NMOSFET's bygate capacitance measurements

Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

Observation of MOSFET degradation due to electrical stressingthrough gate-to-source and gate-to-drain capacitance measurement

The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2-μm effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge     

Separation of interface and nonuniform oxide traps by the DCcurrent-voltage method

Areally nonuniform distribution of oxide charge gives a significant distortion in the gate capacitance and subthreshold DC drain current versus DC gate voltage characteristics. This distortion prevents a reliable determination of the spatial profile of interface and oxide traps generated when a MOS transistor is subjected to channel hot carrier stress. A new procedure is demonstrated which separates the nonuniform oxide charge distribution from interface traps by combining the analysis of two experimental DC characteristics: the subthreshold drain-current and the DC base recombination current versus the gate voltage     

A study of hot carrier degradation in NMOSEET's by gate capacitanceand charge pumping current

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V_g~V_b, V_d/2, V_d. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V_g stress near threshold voltage, the fixed charge is attributed to holes. For high V_g stress, the fixed charge is predominantly electrons. Data for mid V_g stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V_g stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300°C. A post-stress generation of interface traps is observed at low V_g stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.     

Spatially uniform degradation in nMOSFETs: evidence from gatecapacitance and charge pumping current

A linear relationship is found to exist between the decrease in the gate-to-drain capacitance with stress time and the corresponding increase in charge pumping current, in hot-electron stressed nMOSFETs. The result supports a spatially uniform degradation at the Si/SiO₂ interface, that starts within the LDD junction and progresses into the channel     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。     

Theory and experiments on surface 1/f noise

A theoretical low-frequency noise model for the epitaxial-channel surface field-effect structure is presented where random modulation of the channel conductance arises from fluctuation of charges trapped at the oxide trap states near the Si-SiO2interface. In this model, charge fluctuation in the oxide traps arises from carrier tunneling between the fast interface surface states and the oxide trap states. A second fluctuation, at higher frequencies, arises from the random thermal emission and capture of electrons and holes at the fast interface states through the thermal or Shockley-Read-Hall process. Different oxide trap densities were introduced into the interface region of the metal-oxide-silicon field-effect structures using a carefully controlled and reproducible oxygen heat treatment technique. Energy distributions of the oxide trap densities are obtained from capacitance measurements. Humps are observed between the flat band and the onset of strong surface inversion (lower half of the bandgap) in both the noise power and the oxide trap density versus gate voltage (or surface band bending) plots. Theoretical noise power calculations using the experimental oxide trap density profile from the capacitance-voltage data agree very well with the experimental noise humps in both magnitudes and fine structures. It is shown that the frequency spectra of noise depend strongly on the oxide trap density profile in the oxide. It is suggested that the oxide traps are due to the excess oxygen at the SiO2-Si interface.     

Drain-current distortion in CdSe thin-film transistors

CdSe thin-film transistors (TFT's) fabricated with the lift-off process were susceptible to reversible degradation during operation. In particular, when the drain voltage exceeded ∼ 10 V, theI - Vcharacteristics distorted. Current at low drain voltages was depressed, but current at high drain voltages was not. While the TFT was in the distorted state, it was possible by means of pulsed drive on the gate to observe negative differential conductivity. This distortion phenomenon was studied, and its source speculated upon. Factors believed to play a role are formation of deep traps, trapping of hot electrons in the gate insulator, depletion of carriers near the drain electrode, and tunneling of carriers through the depleted region at high drain voltages. Recovery occurs when the trapped electrons in the insulator are released. It is believed that residues of the lift-off process play a role in formation of these traps.     

Subquarter-micrometre elevated source-and-drain MOSFET structureusing polysilicon spacers

A novel subquarter-micrometre MOSFET with a selfaligned source and drain structure is proposed with elevated sources and drains formed by using polysilicon spacers. The spacers can reduce the effective channel length by 50% compared to the mask length, and reduce the junction capacitance by over 30% through a reduction in junction area, as shown by PISCES simulations. A graded oxide spacer is used to decrease the parasitic gate-to-drain capacitance     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Frequency doubling in GaAs/AlGaAs field effect transistor usingreal space transfer

A modified field effect transistor (FET) topology is used which enhances the real space transfer of carrier out of the channel toward a special collector terminal. The drain current rises, peaks, and then reduces as gate voltage is increased due to a steep rise in collector current with gate voltage. When biased near the peak, the AC drain current induced by the gate is folded over becoming frequency doubled. The device exhibits functional multiplexing being operable as either a positive transconductance, negative transconductance, or frequency doubling element setable via quiescent gate voltage     

Channel width dependence of AC stress on bulk nMOSFETs

Channel width dependence of AC stress was investigated. OFF-state stress generated negative interface traps, positive oxide charges, and neutral traps in the whole channel region. Comparison of drain currents of parasitic and main MOSFET during OFF-state indicates that more defects were generated on channel edge than near its center. During ON-state stress, electrons were dominantly trapped in the neutral traps near channel edge. These results cause degradation due to AC stress to become increasingly severe as W is scaled down. The operating voltage to guarantee 10-year lifetime decreased as width decreased. The above results show that electron trapping in neutral traps near the channel edge induce severe degradation on narrow nMOSFET during AC stress. Therefore, degradation of channel edge during AC stress is an importantly considered in narrow nMOSFET.     

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.     

GaAs FET device and circuit simulation in SPICE

We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.     

Electronic properties of Ge nanocrystals for non volatile memory applications

Charge and discharge phenomena of Germanium nanocrystals fabricated by low pressure chemical vapor deposition are investigated by means of Capacitance–Voltage and capacitance decay measurements. The study shows fast programming and erasing times as compared with conventional devices. It is shown that the charge saturation depends on the gate voltage stress in the low electric field regime. For high gate voltages, a saturation of the stored charge is obtained, indicating that the density of trapped carriers in Ge nanocrystals is limited and depends only on the dots size. Capacitance decay measurements exhibits a very long retention time for holes as compared with silicon nanocrystal memories. This is mainly due to the barrier height for holes at the nc-Ge/ ₂ interface. A model for simulation of the retention kinetics has been developed and allows to extract the band alignment of the nc-Ge/SiO₂/Si system. The simulation results are then used to determine the band gap energy of Ge nanocrystals. Finally, it is shown that Ge nanocrystals are very good candidates for P-type Metal Oxide Semiconductor nonvolatile memories.