Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Excimer laser annealed poly-Si thin film transistor with self-aligned lightly doped drain structure

We have made an excimer laser annealed poly-Si thin film transistor (TFT). The stress of the poly-Si films crystallized by excimer laser annealing is studied by Raman spectroscopy. The transverse-optic phonon frequency is independent of the excimer laser energy, but dependant on the precursor a-Si film thickness. The nMOS TFT with a self-aligned lightly doped drain (LDD) structure shows low leakage current. The large leakage current of the pMOS TFT with non-LDD structure is reduced by the off-state stress. The gate to channel capacitance as a function of gate voltage for nMOS TFT shows the characteristic parallel shift of the capacitance–voltage curves with frequency variation.     

Effects of hot-carrier stress on high performance polycrystalline silicon thin film transistor with a single perpendicular grain boundary

This paper is a report on the effect of a single perpendicular grain boundary on the hot-carrier and high current stability in high performance polycrystalline silicon (poly-Si) thin film transistors (TFTs). Under a hot carrier stress condition (Vg = Vth + 1 V, Vd = 12 V), the poly-Si TFT with a single grain boundary is superior to the poly-Si without any grain boundary because of the smaller free carriers available for electric conduction. The shift of transconductance in poly-Si TFT with a single grain boundary is less than 5% after hot carrier stress during a period of 1000 s. The shift of transconductance is about 25% in the case of the poly-Si TFTs without a grain boundary in the channel. On high current stress, the poly-Si TFT without the grain boundary is less degraded than the poly-Si TFT with the grain boundary because the concentrated electric field near the drain junction is lower.     

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.     

Influence of gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors

In this article, the significant effect of a thin gate thermal oxide layer on InGaP/InGaAs doping-channel field-effect transistors (DCFETs) is first demonstrated. When compared to the conventional InGaP/InGaAs DCFET, the device with the gate thermal oxide layer exhibits a higher gate turn-on voltage and nearly voltage-independent transconductances as the gate-to-source is biased form −0.75 V to 0 V, while the maximum transconductance is lower. Experimentally, the transconductance within 90% of its maximum value for gate voltage swing is 1.63 V in the gate-oxide device, which is greater than that of 1.35 V in the device without the gate thermal oxide layer. Furthermore, it maintains a high drain current level at negative gate bias in the gate-oxide device, which can be attributed that the thermal oxide layer with a considerably large energy gap absorbs more of gate negative voltage and the influence of negative voltage on the gate depleted thickness is relatively slight.     

High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates

In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V/sub th/) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low V/sub th/, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.     

Localization effect of a current-path in amorphous In-Ga-Zn-O thin film transistors with a highly doped buried-layer

The highly-doped buried layer (carrier concentration of ~ 10¹⁹ cm^− 3) in an amorphous indium-gallium-zinc oxide (a-IGZO) channel layer of thin film transistor (TFT) led to dramatic improvements in the performance and prolonged bias-stability without any high temperature treatment. These improvements are associated with the enhancement in density-of-states and carrier transport. The channel layer is composed of Ga-doped ZnO (GZO) and a-IGZO layers. Measurements performed on GZO-buried a-IGZO (GB-IGZO) TFTs indicate enhanced n-channel active layer characteristics, such as V_th, μ_FE, I_off, I_on/off ratio and S.S, which were enhanced to 1.2 V, 10.04 cm²/V·s, ~ 10⁻¹³A, ~ 10⁷ and 0.93 V/decade, respectively. From the result of simulation, a current path was well defined through the surface of oxide active layer especially in GB-IGZO TFT case because the highly-doped buried layer plays the critical role of supplying sufficient negative charge density to compensate the amount of positive charge induced by the increasing gate voltage. The mechanism underlying the high performance and good stability is found to be the localization effect of a current path due to a highly-doped buried layer, which also effectively screens the oxide bulk and/or back interface trap-induced bias temperature instability.     

Low temperature short channel polycrystalline silicon thin film transistors with high reliability for flat panel display

We have investigated a short channel (L ≤ 1 μm) effect on the electrical reliability of the low temperature poly-Si thin film transistors (TFT) on a glass substrate. The threshold voltage of the p-type poly-Si TFT was observed to be decreased due to the drain induced barrier lowering as the channel length decreased. In the n-type poly-Si TFT with a lightly-doped-drain (LDD), the threshold voltage was slightly decreased when a high drain voltage was applied, while the field effect mobility decreased due to the series resistance of the LDD region in the short channel poly-Si TFT. As the temperature increased, the field effect mobility increased about 80% due to the increase of the thermal activated carrier concentration. We have also investigated the degradation of a short channel poly-Si TFT under hot carrier and self-heating stress. After hot carrier stress (V_GS = 2V, V_DS = 15V), the field effect mobility was considerably decreased up to 20% due to the trap state generation induced by the hot carrier. The subthreshold slope and threshold voltage were scarcely degraded. After the self-heating stress (V_GS = V_DS = 15V), the subthreshold slope, mobility, and threshold voltage were degraded. Transfer characteristics measured at the high drain voltage (V_DS = 10V) were shifted to a negative direction because of hole trapping at the backside interface between the polysilicon film and buffer oxide on the glass substrate.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

非晶铟锌钨氧化物薄膜晶体管的电学性能和稳定性研究

采用射频磁控溅射法制备了非晶铟锌钨氧化物(a-IZWO)薄膜和以此半导体薄膜为沟道层的薄膜晶体管。研究了沟道宽长比和退火时间对器件电学性能的影响。结果表明,沟道宽长比为400μm:400μm的器件经过120min 200℃空气退火后其电学性能达到最佳,场效应迁移率达到7.29 cm²/Vs,阈值电压为-2.86 V,电流开关比超过10⁷,亚阈值摆幅低至0.13 V/decade。偏压稳定性测试结果证实了器件的偏压稳定性主要受到沟道层缺陷、背沟道表面氧离子和H₂O⁺离子吸附等因素的影响。随着器件沟道宽长比不断增大,退火时间不断延长,器件受到这些因素的影响变小,稳定性越来越好。     

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.     

Effect of hafnium addition on the electrical properties of indium zinc oxide thin film transistors

This study reports the performance and stability of hafnium-indium zinc oxide (HfInZnO) thin film transistors (TFTs) with thermally grown SiO2. The HfInZnO channel layer was deposited at room temperature by a co-sputtering system. We examined the effects of hafnium addition on the X-ray photoelectron spectroscopy properties and on the electrical characteristics of the TFTs varying the concentration of the added hafnium. We found that the transistor on-off currents were greatly influenced by the composition of hafnium addition, which suppressed the formation of oxygen vacancies. The field-effect mobility of optimized HfInZnO TFT was 1.34 cm² V⁻¹ s⁻¹, along with an on-off current ratio of 10⁸ and a threshold voltage of 4.54 V. We also investigated the effects of bias stress on HfInZnO TFTs with passivated and non-passivated layers. The threshold voltage change in the passivated device after positive gate bias stress was lower than that in the non-passivated device. This result indicates that HfInZnO TFTs are sensitive to the ambient conditions of the back surface.     

Current tunnelling through MOS devices

In this study, we have calculated the tunnelling current through ultra thin gate oxides for MOS structure. In the aim to reduce the large gate leakage while scaling SiO₂ down oxide thickness, it has become necessary to use high-k gate dielectrics. We have used HfO₂/SiO₂ dual layer as gate oxide. According to the importance of these alternative gate dielectrics, it becomes essential to take into account the existence of electron trap at the HfO₂/SiO₂ interface. The gate current of n poly-Si/HfO₂/trap/SiO₂/p Si substrate capacitors is underestimated for low voltage if the effect of traps is not taken into account. The influence of trap parameters like width, depth and material masse on gate current has been examined.     

Simulation, fabrication and characterization of ZnO based thin film transistors grown by radio frequency magnetron sputtering

We report the performance of the thin film transistors (TFTs) using ZnO as an active channel layer grown by radio frequency (RF) magnetron sputtering technique. The bottom gate type TFT, consists of a conventional thermally grown SiO2 as gate insulator onto p-type Si substrates. The X-ray diffraction patterns reveal that the ZnO films are preferentially orientated in the (002) plane, with the c-axis perpendicular to the substrate. A typical ZnO TFT fabricated by this method exhibits saturation field effect mobility of about 0.6134 cm2/V s, an on to off ratio of 102, an off current of 2.0 x 10(-7) A, and a threshold voltage of 3.1 V at room temperature. Simulation of this TFT is also carried out by using the commercial software modeling tool ATLAS from Silvaco-International. The simulated global characteristics of the device were compared and contrasted with those measured experimentally. The experimental results are in fairly good agreement with those obtained from simulation.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend

Solution-based indium gallium zinc oxide (IGZO)/single-walled carbon nanotubes (SWNTs) blend have been used to fabricate the channel of thin film transistors (TFTs). The electrical characteristics of the fabricated devices were examined. We found a low leakage current and a higher on/off currents ratio for TFT with SWNTs compared to solution-based TFTs made without SWNTs. The saturation field effect mobility (μ_sat) of about 0.22 cm²/Vs, the current on/off ratio is ~ 10⁵, the subthreshod swing is ~ 2.58 V/decade and the threshold voltage (V_th) is less than − 2.3 V. We demonstrated that the solution-based blend active layer provides the possibility of producing higher performance TFTs for low-cost large area electronic and flexible devices.     

Effect of thickness of ZnO active layer on ZnO-TFT's characteristics

We have investigated the electrical characteristics of ZnO thin film transistors with respect to the thickness of ZnO active layers. The ZnO layers with the thickness of 30 nm to 150 nm were deposited on bottom gate patterned Si substrate by RF sputtering at room temperature. The low-temperature oxide served as gate dielectric. As ZnO channel layer got thicker, the leakage current at V_DS = 30 V and V_G = 0 V greatly increased from 10^− 10 A to 10^− 6 A, while the threshold voltage decreased from 15 V to 10 V. On the other hand, the field effect mobility got around 0.15 cm²/V s except for the 30-nm-thick channel. Overall, the 55-nm-thick ZnO channel layer showed the best performance.     

Stability of indium-oxide thin-film transistors by reactive ion beam assisted deposition

This work reports on the performance and stability of bottom-gate In₂O₃-TFTs with PECVD silicon dioxide gate dielectric. A highly-resistive amorphous In₂O₃ channel layer was deposited at room temperature by reactive ion beam assisted evaporation (IBAE). The field-effect mobility of the n-channel TFT is 33 cm²/V-s, along with an ON/OFF current ratio of 10⁹, and threshold voltage of 2 V. Device stability was demonstrated through measurement of the threshold voltage shift during long-term gate bias-stress and current stress experiments. Device performance, including stability, together with low-temperature processing, makes the indium-oxide TFT an attractive candidate for flexible transparent electronics, and display applications.     

Fabrication of high breakdown voltage silicon Schottky barrier diodes using various edge termination structures

In this work, the design and fabrication of Au/n-Si Schottky barrier diodes (SBDs) with various edge termination schemes, including a reduced-surface-field-type lateral super-junction, a polycrystalline silicon (poly-Si) floating ring, and a p⁺-poly-Si guard ring, are presented. Experimental results show that the reverse leakage current of the proposed SBDs was reduced and the breakdown voltage increased with an increase of the poly-Si width of the guard ring.It was found that the device and fabrication technology developed in the present study is applicable to the realization of SBDs with a high breakdown voltage (≥ 160 V), a low reverse current density (≤ 5.6 μA/cm²), a low forward voltage drop (≤ 5.6 V @ 1 A/cm²), and an adjustable Schottky barrier height of 0.764 to 0.784 eV.     

Effect of reactive sputtered SiOx passivation layer on the stability of InGaZnO thin film transistors

We fabricated the indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with reactive sputtered SiO_x as passivation layer, and investigated the role of the SiO_x passivation layer in the IGZO-TFT under gate bias stress. The bias stability of IGZO-TFT with passivation layer is much better than that of IGZO-TFT without passivation layer. After applying positive bias stress of 20 V for 10000s, the device without passivation layer shows a larger positive V_th shift of 7.3 V. However, the device with passivation layer exhibits a much smaller V_th shift of 1.3 V. It suggests that V_th instability is attributed to the interaction between the exposed IGZO back surface and oxygen in ambient atmosphere during the positive gate voltage stress. The results indicate that reactive sputtered SiO_x passivation layer can effectively improve the bias stability of IGZO-TFT.