A variable threshold voltage inverter for CMOS programmable logiccircuits

A programmable input threshold voltage inverter compatible with double gate transistors fabrication processes is presented. Such a circuit is useful as a programmable input threshold buffer for general purpose circuits that can he included In both TTL and CMOS environments, or can be used as low cost analog programmable comparator. A prototype is fabricated and measured     

The practical engineer [IC design, power reduction]

The need of popular portable electronics for long battery life is placing power reduction at the top of every IC design engineer's to-do list. A new breed of design automation tools is helping them scrimp on power at every step of the VLSI design process. The automation tools can be differentiated, to a first order, by the level of abstraction on which they operate. Lowest of all are the transistor level tools. These possess the best accuracy, but commensurately require the longest run times and have the smallest capacities-the size of the circuit that can be analyzed. While transistor level tools can assist with analyses earlier in the design process, they are typically used to characterize cells and modules for use at the higher abstraction levels. The next level of abstraction embraces the logic-level power analysis tools. The highest abstraction level for which power analysis tools exist today is the architectural level. This type of tool analyzes abstract design representations such as Verilog or VHDL RTL code. The use of these tools in power reduction design is outlined     

An efficient power reduction technique for CMOS flash analog-to-digital converters

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm² without I/O pads.     

应用于数控机床系统的低毛刺12位100MHz电流舵DAC设计

A 12-bit,100-MHz CMOS current-steering D/A converter for CNC(computer number control) systems is presented.To reduce the glitch and increase the SFDR(spurious-free dynamic range),a low crosspoint switch driver and a special dummy switch are applied.In addition,a 4-5-3 segmental structure is used to optimize the performance and layout area.After improvement,the biggest glitch energy decreased from 6.7 pVs to 1.7 pVs,the INL decreased from 2 LSB to 0.8 LSB,the SFDR is 78 dB at a 100-MSPS clock rate and 1 MHz output frequency. This DAC can deliver up to 20.8 mA full-scale current into a 50Ωload.The power when operating at full-scale current is 163 mW.The layout area is 1.8×1.8 mm~2 in a standard 0.35-μm CMOS technology.     

[110]-surface strained-SOI CMOS devices

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.     

Precise FPN compensation circuit for CMOS APS [imager]

Fixed pattern noise (FPN) is one of the major disadvantages of CMOS imagers in comparison with CCD imagers. A simple and precise FPN compensation circuit for a CMOS active pixel sensor (APS) imager with an in-line non-destructive readout function is presented     

High-performance metal/silicide antifuse [for CMOS technology]

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Ω, which is a factor of 10 less than that of Si-based antifuses (poly/n⁺ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory     

基于GSAA算法的组合电路最大功耗估计方法

最大功耗估计问题是一个NP难题。提出的方法利用遗传模拟退火算法(GSAA)在整个解空间快速搜索问题的最优解，实现组合电路最大功耗的快速、精确估计。仿真结果表明，提出的方法比基于遗传算法(GA)的估计方法在估算精度和收敛速度上都有提高，适合于大规模组合电路最大功耗的估计。     

Beating the heat [CMOS hot-carrier reliability]

CMOS hot-carrier reliability at both transistor and circuit levels has been examined. Accurate reliability assessment requires defining suitable criteria for acceptable performance for both circuit and individual transistors. As device designers meet demands for greater speed and more complex circuitry accompanied by shrinking the size of transistor into the deep-submicron regime, they have to contend with increase in current densities and higher electric fields. Though in general a MOSFET's driving capability increases as the channel length decreases, the resulting high field will eventually limit the driving capability of the device. The authors discuss improving CMOS hot-carrier reliability through analysis, modelling and simulation     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

Moore's law lives on [CMOS transistors]

We discuss several device structures suitable for scaling CMOS devices well into the nano-CMOS era, perhaps down below 10 nm physical gate length. The ultra-thin body MOSFET device structure has many features in common with today's bulk MOSFET, which makes it easier for industry to introduce into manufacturing. On the other hand, the double-gate structure as represented by the FinFET appears to offer greater scalability down to 10 nm gate length or perhaps even below. While a number of significant challenges remain to be overcome, including device parasitics, interfaces, and threshold voltage control techniques, it appears that the continued evolution of CMOS integrated circuit technology into this regime will not be impeded by basic limitations of the underlying transistor technology. The implication of this is that "Moore's law" may continue for yet another 15-20 years before the ultimate device limits for CMOS are reached.     

Threshold-voltage balance for minimum supply operation [LV CMOS chips]

The difference between the threshold voltages V/sub t/ of pMOS and nMOS transistors is a critical issue in the low-voltage operation of CMOS circuits. The pMOS/nMOS V/sub t/ balancing profit is analyzed in terms of subthreshold leakage current and the performance of CMOS LSIs and the minimum supply voltage of logic circuits. Matching the pMOS/nMOS V/sub t/ improves LSI performance and reduces the lowest supply voltage by 0.15 V. We propose a new concept of body bias management that uses forward biasing, fluctuation compensating, and V/sub t/ matching technologies to resolve the issue.     

A 1-V programmable DSP for wireless communications [CMOS]

In an effort to extend battery life, the manufacturers of portable consumer electronics are continually driving down the supply voltages of their systems. For example, next-generation cellular phones are expected to utilize a 1-V power supply for their digital component. To address this market, an energy-efficient, programmable digital signal processing (DSP) chip that operates from a 1-V supply has been designed, fabricated, and tested. The DSP features an instruction set and micro-architecture that are specifically targeted at wireless communication applications and that have been carefully optimized to minimize power consumption without sacrificing performance. The design utilizes a 0.35-μm dual-V_t technology with 0.25-μm minimum gate lengths that enables good performance at 1 V. Specifically, the chip dissipates 17 mW at 1 V, achieving 63-MHz operation with a power-performance metric of 0.21 mW/MHz     

Efficient rough-set-based attribute reduction algorithm with nearest neighbour searching

A fast nearest neighbour searching method with gradually shrinking search space is proposed to reduce the computing complexity of indiscernibility relation in the rough-set-based attribute reduction algorithm. Experimental results show that the proposed algorithm computed attribute reduction more efficiently     

The power within [Internet]

The public Internet has revolutionised the world's communications. Now companies are rushing to build their own private intranets. The author explains some of the attractions that intranets provide: cross-platform functionality; a consistent view of information; an enabling technology path; ease of integration; ease of communication; relatively low-cost installation; and increased effectiveness of information     

Nonstop monitoring [power quality]

A power failure could spell disaster for a large financial institution. The author describes the role of fixed power quality monitoring systems in ensuring that the trading never has to stop. Consulting engineers and site facility managers are increasingly of the opinion that supply quality in a modern commercial building demands the installation of a fully integrated, fixed power quality monitoring system, operating 24 hours a day, 365 days a year. The PegaSys system, manufactured in Canada by Power Measurement Ltd of Victoria, British Columbia, and marketed in the UK by C-Matic Systems is an example of a modern, highly flexible, power monitoring system. A typical installation consists of one or more monitoring PCs connected to a network of fixed power quality instruments installed at all of the key supply points throughout a building. The PC's graphical interface depicts the electrical layout of the building, indicating the location of each monitoring instrument, together with the status of load levels or approaching alarm limits. Typically, a user will have one main screen where system condition can be viewed at a glance. More detailed information is available by navigating down through the hierarchy of screen layers. The objective of the system is to provide load trending for system planning together with pre-fault alarming, so that, as far as is humanly possible, power outages are avoided