点阵液晶模块与LPC2214的接口方式研究与编程

该文从应用角度叙述了常规的液晶显示模块YM19264C的结构特点和基本功能,并在YM19264C和ARM嵌入式微控制器LPC2214时序分析的基础上,讨论了ARM嵌入式微处理器LPC2214与点阵液晶显示模块组成的硬件电路的设计方法,设计了以I/O模拟总线连接液晶模块和外部存储器接口扩展液晶模块两种应用电路,而且对两种接口方式下的程序设计进行了分析,同时,给出了屏幕显示不正常时一个简单的解决办法。     

A formal framework for modeling and validating Simulink diagrams

Simulink has been widely used in industry to model and simulate embedded systems. With the increasing usage of embedded systems in real-time safety-critical situations, Simulink becomes deficient to analyze (timing) requirements with high-level assurance. In this article, we apply Timed Interval Calculus (TIC), a real-time specification language, to complement Simulink with TIC formal verification capability. We elaborately construct TIC library functions to model Simulink library blocks which are used to compose Simulink diagrams. Next, Simulink diagrams are automatically transformed into TIC models which preserve functional and timing aspects. Important requirements such as timing bounded liveness can be precisely specified in TIC for whole diagrams or some components. Lastly, validation of TIC models can be rigorously conducted with a high degree of automation using a generic theorem prover. Our framework can enlarge the design space by representing environment properties to open systems, and handle complex diagrams as the analysis of continuous and discrete behavior is supported.     

Complete high-performance cache system for the 80386

The 80386 is a high-performance third-generation microprocessor that is now standard in most top-of-the-range PCs. Like all similar processors operating at clock rates above 30 MHz, the 80386 must use cache memory if it is to operate efficiently. Without cache memory, the user must either pay a very high price for very fast RAM or employ slower memory by introducing wait states. This application note describes the 80386 bus interface and demonstrates how it can be interfaced to IDT cache tag RAMs to create a cache system. Although the report describes a relatively basic cache system, it covers all design considerations ranging from system timing to the programming of the PALs needed to implement the interface. A.C.     

High-speed block-diagram languages for microprocessors and minicomputers in instrumentation,control and simulation

Block-diagram languages implement instrumentation, control and simulation programs in terms of analog-computer-like block diagrams. Block-operators, which range from simple adders to complete real-time controllers and amplitude-distribution analyzers, are assembly-language macros, ROM subroutines or microprograms. Block-diagram languages are readily accepted by engineers, who need not learn assembly language and can still obtain essentially optimal execution speed on small machines. Block-diagram-programmed minicomputers can beat a CDC 6400 using FORTRAN, and microprocessor execution is much more efficient than PL/M. Machine independent block-diagram programs are sorted and cross-translated by optimizing translators, which eliminate redundant memory references. Efficient block-operator macros, subroutines or microprograms are written once and for all by computer specialists, but new operators can be added at will. This paper discusses an optimal minicomputer translator, an interactive microcomputer system using BASIC to generate and test block-diagram programs, hand-translation for small microprocessor programs and some applications.     

Design considerations for a hardware-refreshed memory card for the MC68000

Circuit complexity is the main disadvantage of using hardware rather than software to refresh dynamic RAM. Program overheads, withdrawal of interrupts from use, and increased demands on system components other than the microprocessor militate against the software solution. A hardware-refreshed 256 kbyte dynamic RAM card has been developed for use with 68000-based systems. The design includes a TMS 4500AML controller and a TMS 4164 64k dynamic RAM. The operation of the dynamic RAM is explained. The RAM is interfaced to the 68000 by the system's VME bus. The organization of the memory is discussed, and the steps in a software routine to test blocks of memory are outlined.     

TL7700 voltage supervisor

It is only to be expected that the microprocessor has grabbed almost all the limelight. Hardly a month goes by without some major advance in microprocessors being announced. However, there is also a continual introduction of major new peripherals. With all the glamorous competition, interesting developments in more humble components are often overlooked. This note presents the TL7700 supply voltage supervisor. This is a simple device that performs two functions and saves a handful of discrete components. It executes the power-on-reset function required by most microprocessors and also acts as a power supply monitor that resets the microprocessor if the voltage falls below a predetermined level. This function is useful in high-volume, e.g. automotive, applications, where cost is highly important. The power supply monitoring circuit is essential in applications where there is ‘housekeeping’ to be done before the supply collapses. Another useful application of the device is the protection of battery back-up memory.     

Timing consistency checking for UML/MARTE behavioral models

UML/MARTE model-driven development approaches are gaining attention in developing real-time embedded software (RTES). UML behavioral models with MARTE annotations are used to describe timing behaviors and timing characteristics of RTES. Particularly, state machine, sequence, and timing diagrams with MARTE annotations are appropriate to understand and analyze timing behaviors of RTES. However, to guarantee software correctness and safety, timing inconsistencies in UML/MARTE should be identified in the design phase of RTES. UML/MARTE timing inconsistencies are related to modeling errors and can be hazards throughout the lifecycle of RTES. We propose a systematic approach to check timing consistency of state machine, sequence, and timing diagrams with MARTE annotations for RTES. First, we present how state machine, sequence, and timing diagrams with MARTE annotations specify the behaviors of RTES. To overcome informal semantics of UML/MARTE models, we provide formal definitions of state machine, sequence, and timing diagrams with MARTE annotations. Second, we present the timing consistency checking approach that consists of a rule-based and a model checking-based timing consistency checking. In the rule-based timing consistency checking, we validate well formedness of UML/MARTE behavioral models in timing aspects. In the model checking-based timing consistency checking, we verify whether timing behaviors of sequence and timing diagrams with MARTE annotations are consistent with the timing behaviors of state machine diagrams with MARTE annotations. We support an automated timing consistency checking tool UML/MARTE timing Consistency Analyzer for a seamless approach. We demonstrate the effectiveness and the practicality of the proposed approach by two case studies using cruise control system software and guidance and control unit software.     

Pentium4处理器的内存层次分析

处理器存储系统的效率对其整体性能有着十分重要的作用。文中介绍了P4处理器内存的体系结构，它包括一级数据Cache、二级Cache、Trace Cache；各部分完成的功能以及为提高命中率和降低存取时间，从而提高效率而采取的预取处理机制；P4处理器主要采取具有层次结构的内存设计、大容量的二级Cache和在跟踪Cache中采用预取处理机制的方法来提高Cache的命中率和降低未命中的代价来缩短处理器的访问时间，最终达到提高处理器整体性能的目的。     

Timing Diagrams: Formalization and Algorithmic Verification

Timing diagrams are popular in hardware design. They have been formalized for use in reasoning tasks, such as computer-aided verification. These efforts have largely treated timing diagrams as interfaces to established notations for which verification is decidable; this has restricted timing diagrams to expressing only regular language properties. This paper presents a timing diagram logic capable of expressing certain context-free and context-sensitive properties. It shows that verification is decidable for properties expressible in this logic. More specifically, it shows that containment of -regular languages generated by Büchi automata in timing diagram languages is decidable. The result relies on a correlation between timing diagram and reversal bounded counter machine languages.     

CAN智能适配卡的设计方案

本介绍了发电机状态监测仪中CAN智能适配卡的功能和硬件组成,详细讨论了ISA总线及单片机对双口RAM的地址空间的分配。针对ISA总线和卡上单片机同时对双口RAM读写数据时的仲裁问题,提出了一种硬件判优的实现方法。并对适配卡的软件设计进行了总体上的阐述。     

Memories in microprocessor systems

The second article in this series discusses the approaches to address decoding needed to enable the wide range of memory components (described in a previous article) to be interfaced to a microprocessor. The simplest form, partial address decoding, is considered in detail, using the Motorola MEK 6800D1 evaluation kit as an example.     

高性能RISC微处理器硬件仿真器设计

在微处理器设计中,为了系统级软硬件协同仿真,在后端设计前必须采用硬件仿真器对设计进行系统验证．为此,采用FPGA设计32位RISC流水线结构微处理器的硬件仿真器．此设计主要包括以下特点：采用内存管理单元(MMU)可以实现虚拟地址管理;包括片上Cache,其中包括指令Cache(I-Cache)和数据Cache(D-Cache);采用标准SYSAD接口设计;包括片上乘除处理单元(MDU);实现精确异常处理．设计采用XILINX公司的xc2v2000实现,其工作频率为30MHz．     

Specification and analysis of timing requirements for real-time systems in the CBD approach

In real-time software, not only computation errors but also timing errors can cause system failures, which eventually result in significant physical damages or threats to human life. To efficiently guarantee the timely execution of expected functions, it is necessary to clearly specify and formally verify timing requirements before performing detailed system design. With the expected benefit of reusability and extensibility, component technology has been gradually applied to developing industrial applications including real-time systems. However, most of component-based approaches applied to real-time systems lack in a systematic and rigorous approach to specifying and verifying timing requirements at an earlier development stage. This paper proposes a component-based approach to specifying and verifying timing requirements for real-time systems in a systematic and compositional manner. We first describe behaviors of the constituent components including timing requirements in UML diagrams, and then translate the UML diagrams into MTER nets, an extension of TER nets, to perform timing analysis in a compositional way. The merit of the proposed approach is that the specification and analysis results can be reused and independently maintained.     

The 68040 processor. 2. Memory design and chip

For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The MOVE16 instruction, which moves a cache line from one address (which may reside in the data cache) to another address outside the cache is described. User testing, based on dedicated test logic that is fully compliant with the IEEE 1149.1 standard, and factory testing, for which the processor employs structured design techniques for random logic and special test modes for embedded arrays, are examined. The use of top-down design and a hierarchical method of design verification is discussed     

用C8051F020的SPI接口扩展大容量数据存储器

本文介绍了一种利用串行外设接口(SPI)为SOC单片机C8051F020扩展大容量数据存储器的设计方案,并给出来软件流程图和示例。该方案充分利用了SPI的功能,在极少地占用单片机引脚的情况下,实现了数据存储器的扩展。     

基于增加数据宽度的方法提高访存速度

低效率的访存操作是限制微处理器性能提高的一个关键因素。因此提高访存速度可以有效改善微处理器的性能。提出了一种基于增加数据宽度的方式来提高访存速度的方法。通过使用多字宽存储器来增加数据带宽,降低失效开销的时钟周期,从而达到提高访存效率的目的。     

Software-controlled memory duplication

The design and implementation of software-controlled memory duplication are described. A simple way of duplicating the memory capacity of any microprocessor is presented. As an example the duplication of the 64 kbyte capacity of an 8-bit microprocessor is considered.     

MUMS–A Reconfigurable Microprocessor Architecture

The would-be microprocessor user is currently confronted with a large and increasing number of different devices, each characterized by a unique architecture, instruction set, and hardware conventions, and provided with a varying, usually small degree of software support. Consequently, microprocessor systems reflect to a major extent the hardware and software idiosyncracies of the specific microprocessor(s) they incorporate; any attempt to replace a microprocessor with a newer or improved type, however inexpensive, entails a major system redesign. The work described in this article–MUMS, for Modular-Unified-Microprocessor-System–is an ongoing research project to overcome these limitations, having a modular, standardized, and versatile structure that is nevertheless commensurate with the low cost of the microprocessors themselves. Basic to this idea is a relatively simple micro-bus (the MUMS bus) that carries generic signals only, and over which a microprocessor communicates with its environment. Each microprocessor and all other modules, whether memory or I/O devices, connect to the MUMS bus through simple interfaces that standardize to the bus protocol. Simplicity is retained by having one microprocessor per MUMS bus, but flexibility is provided by allowing for MUMS busses to connect through a communications unit for the purpose of interprocessor communication or shared resources, or both. By this technique MUMS can be used in a standalone configuration or in conjunction with other processors. The insertion of a new nicroprocessor requires only one new MUMS bus interface and an associated software utility package in a ROM module; the rest of the system is unmodified.     

一种基于Simics的兼容微处理器系统级验证平台

高性能微处理器复杂度不断增大,验证也变得更为复杂,已成为设计过程中的瓶颈。文章就兼容微处理器的验证,提出了基于Simics构建系统级验证平台的一种设计方法。通过自行开发的控制模块把Simics提供的ISS(InstructionLevelSimulator)和相关的存储器模型、外围设备与外部仿真器相连构建了一个验证系统平台。在这个平台中Simics支持的处理器作为待验证兼容处理器的参考模型,测试使用的激励来自真实的操作系统和应用程序,自动比较运行结果。借助于Simics的快速仿真速度和现场恢复能力,该平台可大大加快验证速度。     

GaAs microprocessors and digital systems: an overview of R&D efforts

An overview is provided of existing gallium arsenide microprocessors and related digital designs. The architectures described cover a wide range of applications and were chosen on the basis of their unique design and technology characteristics. The issues considered relate to the processor-design level with some register-transfer-level components covered for the sake of completeness. The discussion covers general-application microprocessors including: RCA 8-bit microprocessor; CDC 32-bit microprocessor; McDonnell Douglas 32-bit microprocessor; and RCA 32-bit microprocessor microprocessors of symbolic applications including: Carnegie Mellon's RISCF; and GAELIC from Magnavox, systolic array processors, and alternative approaches to processor design.<>