Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic     

Digital‐Inverter Amine Sensing via Synergistic Responses by n and p Organic Semiconductors

Chemiresistors and sensitive organic field‐effect transistors (OFETs) have been substantially developed as cheap, scalable, and versatile sensing platforms. While new materials are expanding OFET sensing capabilities, the device architectures have changed little. Higher order logic circuits utilizing OFETs sensitive to amine vapors are presented. The circuits depend on the synergistic responses of paired p‐ and n‐channel organic semiconductors, including a rare analyte‐induced current increase by the n‐channel semiconductor. This is the first step towards ‘intelligent sensors’ that utilize analog signal changes in sensitive OFETs to produce direct digital readouts suitable for further logic operations.     

Hybrid Nanodielectrics for Low‐Voltage Organic Electronics

Nanoscale hybrid dielectrics composed of an ultra‐thin polymeric low‐κ bottom layer and an ultra‐thin high‐κ oxide top layer, with high dielectric strength and capacitances up to 0.25 μFcm^?2, compatible with low‐voltage, low‐power, organic electronic circuits are demonstrated. An efficient and reliable fabrication process, with 100% yield achieved on lab‐scale arrays, is demonstrated by means of pulsed laser deposition (PLD) for the fast growth of the oxide layer. With this strategy, high capacitance top gate (TG), n‐type and p‐type organic field effect transistors (OFETs) with high mobility, low leakage currents, and low subthreshold slopes are realized and employed in complementary‐like inverters, exhibiting ideal switching for supply voltages as low as 2 V. Importantly, the hybrid double‐layer allows for a neat decoupling between the need for a high capacitance, guaranteed by the nanoscale thickness of the double layer, and for an optimized semiconductor–dielectric interface, a crucial point in enabling high mobility OFETs, thanks to the low‐κ polymeric dielectric layer in direct contact with the polymer semiconductor. It is shown that such decoupling can be achieved already with a polymer dielectric as thin as 10 nm when the top oxide is deposited by PLD. This paves the way for a very versatile implementation of the proposed approach for the scaling of the operating voltages of TG OFETs with very low level of dielectric leakage currents to the fabrication of low‐voltage organic electronics with drastically reduced power consumption.     

Understanding,Optimizing, and Utilizing Nonideal Transistors Based on Organic or Organic Hybrid Semiconductors

Many advanced materials have been developed for organic field‐effect transistors (OFETs) or thin‐film transistors (TFTs) based on organic and organic hybrid materials. However, although many new OFETs exhibit superior characteristic parameters (such as high mobility), most of them show nonideal performances that have strongly limited progress in the design of molecules, the understanding of transport mechanisms, and the circuit applications of OFETs. In this review, the device physics of ideal and nonideal OFETs is discussed first to understand the factors that limit effective mobility in semiconducting channels, distort the potential distribution, or reduce the drift electric field. Then, recent advances in optimizing the material combinations, device structures, and fabrications of OFETs toward ideal transistors are discussed. Based on the good control of materials and interfaces, some new and novel concepts to utilize the nonideal properties of OFETs to build low‐power circuits and integrated sensors are also discussed.     

A Phase Interpolator CDR with Low-Voltage CML Circuits

In this paper, a phase interpolator clock and data recovery (CDR) with low-voltage current mode logic (CML) latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.     

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.     

Flexible nano-hybrid inverter based on inkjet-printed organic and 2D multilayer MoS2 thin film transistor

We report a novel platform on which we design a flexible high-performance complementary metal–oxide–semiconductor (CMOS) inverter based on an inkjet-printed polymer PMOS and a two-dimensional (2D) multilayer molybdenum disulfide (MoS₂) NMOS on a flexible substrate. The initial implementation of a hybrid complementary inverter, comprised of 2D MoS₂ NMOS and polymer PMOS on a flexible substrate, demonstrates a compelling new pathway to practical logic gates for digital circuits, achieving extremely low power consumption with low sub-1 nA leakage currents, high performance with a voltage gain of 35 at 12 V supply voltage, and high noise margin (larger than 3 V at 12 V supply voltage) with low processing costs. These results suggest that inkjet-printed organic thin film transistors and 2D multilayer semiconducting transistors may form the basis for potential future high performance and large area flexible integrated circuitry applications.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

CMOS NAND and NOR Schmitt circuits

Original solutions of m-input NAND and NOR logic circuits with hysteresis in the transfer characteristics are proposed. Multiple inputs are done similarly to standard NAND and NOR logic circuits. The logic circuits proposed in this paper consist of 2m + 1 paris of enhancement CMOS transistors. The hysteresis voltage depends on supply voltage and transistor geometry. The proposed solutions always guarantee hysteresis, even with very large process variations. The noise immunity is typically greater than 50% of supply voltage. Analysis using simple device models together with computer simulations and experimental results is given.     

Organic Field‐Effect Transistors and Unipolar Logic Gates on Charged Electrets from Spin‐On Organosilsesquioxane Resins

Controllable shifting of threshold voltage and modulation of current in organic field‐effect transistors (OFETs) is demonstrated, resulting in the formation of unipolar inverters by making use of space‐charge electrets. Prior to the deposition of the organic semiconductor (OSC), negative corona charges are injected and trapped in the bulk of the organosilsesquioxane glass resin gate dielectrics. The effective surface potential is controlled by the corona‐charging and subsequent annealing process. It is found that the shift of the transfer characteristics is governed by the electrostatic induction effects of the charged gate electrets, and this observed shift can be related to the surface potential of the layer next to the transistor channel. The process control, efficiency, and long‐term stability of charge storage in spin‐on organosilsesquioxane glass resins are sufficient to enable the construction of simple unipolar inverters and to allow for circuit tuning. New OFET unipolar inverters with an enhancement‐mode driver and a depletion‐mode load are presented, composed of only two simple OFETs with the same channel dimensions and the same p‐type OSC on charged electrets. This design allows the implementation of full‐swing organic logic circuits and illustrates a potential process simplification for organic electronics.     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.     

Vertical Organic Field‐Effect Transistors

Field‐effect transistors are the fundamental building blocks for electronic circuits and processors. Compared with inorganic transistors, organic field‐effect transistors (OFETs), featuring low cost, low weight, and easy fabrication, are attractive for large‐area flexible electronic devices. At present, OFETs with planar structures are widely investigated device structures in organic electronics and optoelectronics; however, they face enormous challenges in realizing large current density, fast operation speed, and outstanding mechanical flexibility for advancing their potential commercialized applications. In this context, vertical organic field‐effect transistors (VOFETs), composed of vertically stacked source/drain electrodes, could provide an effective approach for solving these questions due to their inherent small channel length and unique working principles. Since the first report of VOFETs in 2004, impressive progress has been witnessed in this field with the improvement of device performance. The aim of this review is to give a systematical summary of VOFETs with a special focus on device structure optimization for improved performance and potential applications demonstrated by VOFETs. An overview of the development of VOFETs along with current challenges and perspectives is also discussed. It is hoped that this review is timely and valuable for the next step in the rapid development of VOFETs and their related research fields.     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits     

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity are common approaches used in conventional CMOS. In adiabatic switching circuits, the current flow through transistors can be significantly reduced by ensuring uniform charge transfer over the entire available time. This paper presents the simulation of this current in two-phase clocked adiabatic static CMOS logic (2PASCL) and conventional CMOS. From the SPICE simulations, at transition frequencies from 1 to 12 MHz, a 4×4-bit array 2PASCL multiplier shows a maximum reduction in power dissipation of 77% relative to that of a static CMOS. The measurement results of a 4×4-bit array 2PASCL multiplier demonstrate a 57% reduction compared to a 4×4-bit array two-phase clocked adiabatic dynamic CMOS logic (2PADCL). These results indicate that 2PASCL technology can be advantageous when applied to low-power digital devices operated at low frequencies, such as radio-frequency identification (RFID) tags, smart cards, and sensors.     

Superintegrated voltage clamp

A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device. Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads. Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers.     

一种低电压、高增益电荷泵

电荷泵在低压电路中扮演着重要的角色。作为片上电荷泵,其面临的主要问题是：电压增益、电压纹波和面积效率。该文提出了一种新型的电荷泵电路,它采用辅助电荷泵、电平转移电路结构来产生不同摆幅的时钟,该时钟被用来驱动开关管的栅极,以有效控制开关管的电导,提高电压增益。由于采用PMOS管作为开关管,传输过程中避免了阈值电压损失。仿真结果显示,与以往文献中提到的电荷泵结构相比,该电荷泵具有更高的电压增益,开启时间短,纹波小,在低压应用环境优势更为突出。     

Polymer Dielectrics and Orthogonal Solvent Effects for High‐Performance Inkjet‐Printed Top‐Gated P‐Channel Polymer Field‐Effect Transistors

We investigated the effects of a gate dielectric and its solvent on the characteristics of top‐gated organic field‐effect transistors (OFETs). Despite the rough top surface of the inkjet‐printed active features, the charge transport in an OFET is still favorable, with no significant degradation in performance. Moreover, the characteristics of the OFETs showed a strong dependency on the gate dielectrics used and its orthogonal solvents. Poly(3‐hexylthiophene) OFETs with a poly(methyl methacrylate) dielectric showed typical p‐type OFET characteristics. The selection of gate dielectric and solvent is very important to achieve high‐performance organic electronic circuits.