a-Si:H/a-SiN_x:H多层膜界面的研究

<正> 尽管过去几年对非晶半导体多层膜及其界面对多层膜传输性能影响的研究甚多,然而对于界面缺陷态的特性及其密度了解甚少。不同的测量方法得到的a-Si:H/a-SiNx:H界面缺陷态密度可从1010变到1012cm-2。这一实验结果反映了每一测试方法仅能探测某些能级的缺陷,在某些情况下可能是不同类的缺陷。非晶硅系材料都包含有氢。已发现,在多层膜的沉积过程中,由于组成多层膜的子层间应力释放的需要以及两子层材料的氢扩散系数不同而     

Study of thermal equilibration in selenium- and sulphur-doped a-Si:H

The present paper reports the thermal equilibration in selenium- and sulphur-doped hydrogenated amorphous silicon thin films deposited by plasma-enhanced chemical vapour deposition. The conductivity of Se- and S-doped a-Si:H is observed to be very sensitive to the rate at which the samples are cooled following the high temperature anneal. Arrhenius plots of conductivity for various doped films revealed thermal equilibration above the equilibration temperature, T _E, thus accounting for larger activation energies. The barrier energy is lower for a-Si,Se:H than for a-Si,S:H, due to a higher defect density in S-doped films.     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiN_x:H Film

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Dependence of Threshold Voltage of a-Si:H TFT on a-SiNx:H Film^①

The relation between threshold voltage for hydrogenated amorphous silicon thin film transistors(a-Si:HTFTs)and deposition conditions for hydrogenated amorphous silicon nitride(a-SiNx:H)films is investigated.It is observed that the threshold voltage,Vth,of a-Si:HTFT increases with the increase of the thickness of a-SiNx:H film,and the threshold voltage is reduced apparently with the increase of NH3/SiH4 gas flow rate ratio.     

氢化非晶硅局域态电荷密度的解析统一模型

本文发展了一种简明的氢化非晶硅局域态电荷密度统一模型。从ａ－Ｓｉ材料的带隙态密度适配参数分布函数出发，采用Ｓｈｏｃｋｌｅｙ－Ｒｅａｄ－Ｈａｌｌ统计描述，推导出局域态电荷密度统一的解析表达式，该模型同时考虑了带尾局域态和缺陷局域态的作用。     

Flexible a-Si:H Position-Sensitive Detectors

Flexible and large area (5 mm /spl times/80 mm with an active length of 70 mm) position-sensitive detectors (PSDs) deposited onto polymeric substrates (polyimide-Kapton VN) have been fabricated. The optimized structure presented is based on a heterojunction of amorphous silicon (a-Si:H)/ZnO:Al. The sensors were characterized by spectral response, photocurrent dependence as a function of light intensity, and position detection measurements. The set of data obtained on one-dimensional PSDs based on the heterojunction show excellent performances with a maximum spectral response of 0.12 A/W at 500 nm and a nonlinearity of /spl plusmn/10% over 70-mm length. The produced sensors present a nonlinearity higher than those ones produced on glass substrates, due to the different thermal coefficients exhibited by the polymer and the a-Si:H film. In order to prove this behavior, it was measured the defect density obtained by the constant photocurrent method on a-Si:H thin films deposited on polymeric substrates and bent with different radii of curvature.     

Modification of GaAs Schottky barriers using a-Si:H interfaciallayers

The electrical characteristics of metal/a-Si:H/n-GaAs diode structures were studied in order to investigate the role of the a-Si:H and the claim of no barrier at the GaAs/a-Si:H interface. Diodes were fabricated using a-Si:H layers between 30 and 1920 Å thick, with Al and Mg metallization, and the current-voltage and capacitance-voltage characteristics were examined. Rectifying Schottky barriers were formed at Al/a-Si:H junctions, while good ohmic contacts were formed at Mg/a-Si:H junctions, enabling effects due to the metal/a-Si:H and a-Si:H/GaAs interface to be isolated. A dramatic increase in the forward turn-on voltage was observed as the thickness of the a-Si:H layer increased. The diode behavior can be explained by considering three effects in series: (1) an a-Si:H/GaAs barrier of about 0.6 eV, consistent with Fermi-level pinning in GaAs; (2) a metal/a-Si:H barrier, dependent on the metallization; and (3) space-charge-limited current (SCLC) in the bulk a-Si:H. The SCLC effectively gives rise to a voltage-dependent resistance and causes the increased turn-on voltages     

Optical and electrical current gain in an amorphous silicon bulk barrier phototransistor

An amorphous silicon (a-Si) bulk barrier phototransistor was successfully fabricated on a glass substrate. The measured optical gain G and electrical current gain HFEare 196 percent and 11.8, respectively. Estimation and measurement methods for G and HFEare discussed.     

Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.      

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

a-Si:H Schottky gate on n-GaInAs

The metal Schottky contact leads to low barrier heights on small-gap (<1 eV) semiconductors. This is the case of the n-type GaInAs material matched to InP where this barrier does not exceed 0.3 eV. We have found an original method to improve this result considerably by using a deposition of an amorphous semiconductor a-Si or a-Si: H. A Pt metal acts as the Schottky contact on the amorphous layer. The device behaves like a heterostructure of a high-gap (amorphous layer: Eg?1.8 eV) on a small-gap (GaInAs:0.75 eV) material. The Schottky-barrier height (0.8 eV) is greater than the GaInAs bandgap (0.75 eV). The reverse current is very low: 20 nA at 1 V reverse voltage for a 0.6 mm diode diameter. An FET using a-Si: H as a gate realised on a GaInAs layer shows a good electrical characteristic.     

非晶硅薄膜的应用前景

本文评述并探讨了-Si:H薄膜在电子学领域的种种应用。-Si:H太阳电池是非晶硅薄膜的最重要的器件,目前的主要研究课题仍是改进材料性质和器件参数,以提高电池的能量转换效率。利用-Si:H灵敏的光敏效应记录图象信息,可能有广阔的应用前景(如用于摄象管和静电复印等)。以-Si:H场效应管为基础的集成电路,易于实现大面积和结构的立体化,因此有很大吸引力。-Si:H FET驱动的液晶大面积显示和材料本身的场致发光在大面积平面显示中直接应用的可能性亦引人注目。以整流、检测等为目的的其它-Si:H二极管也都具有相当的价值。     

Ion implanted contacts to a-Si:H thin-film transistors

Fabrication steps to improve ion implanted source-drain contacts to hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) have been determined. After establishing a contact performance baseline using devices made with Al/intrinsic a-Si:H contacts, improvements were made to the metal/a-Si:H contact scheme using unheated and heated implants, single- and double-level phosphorous implants, a buffered HF acid dip just prior to metal deposition, Al and Al-Si-Cu metallization schemes, and a post-metallization anneal.     

a-SiH 热处理过程中纳米硅粒尺寸的控制(英文)

报道了控制热处理过程中含氢非晶硅中纳米硅颗粒大小的一种新方法。用喇曼散射、X射线衍射和计算机模拟,发现在非晶硅中所形成的纳米硅颗粒的大小,随着热退火过程中升温速率的变化而变化。在退火过程中,若非晶硅薄膜升温速率较高(～100℃/s),则所形成纳米硅粒的大小在1.6～15nm;若非晶硅薄膜升温速率较低(～1℃/s),则纳米硅粒大小在23～46nm。根据晶体生长理论,讨论了升温速率的高低与所形成的纳米硅颗粒大小的关系。     

Characteristic lengths for steady-state transport in illuminated,intrinsic a-Si:H

The steady-state transport equations are solved for a general small-signal case. This solution leads to the spatial distribution of the carriers in the bulk of undoped hydrogenated amorphous silicon (a-Si:H) under illumination. The general small-signal differential equations for electrons and holes, including a local and/or external electric field, are first established. Subsequently, the analysis is restricted to the case with a negligible external electric field. Two characteristic lengths appear in the analytical solution. They are interpreted for the lifetime regime as the ambipolar diffusion length and the dielectric relaxation length. Depending on the material parameters, one or the other of these lengths dominates the transport. Illustrative numerical examples for typical solar-cell-quality a-Si:H are given     

On the quality of contacts in a-Si:H staggered electrode thin-film transistors

Amorphous silicon thin-film field-effect transistors have been made with a staggered electrode structure. In this structure we distinguish two separate contributions to the total contact resistance, namely, the Al/a-Si:H barrier itself and the bulk resistance of the underlying a-Si:H layer. Concerning the first contribution it was found that a P-implantation forming n⁺regions followed by post-metallization annealing (PMA) at a moderate temperature of 200°C is very efficient in reducing the resistance of the Al contacts to negligibly small values. The second contribution, i.e., the bulk resistance, implies a variable series resistance in field-effect (FE) measurements. Thin-film transistors (TFT's) with different gate lengths were used for the first time to determine this residual series resistance Rres.     

A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs

This letter presents a novel pixel circuit for hydrogenated amorphous silicon (a-Si:H) active matrix organic light-emitting diode displays employing the short-term stress stability characteristics of a-Si:H thin film transistors (TFTs). The pixel circuit uses a programming TFT that is under stress during the programming cycle and unstressed during the drive cycle. The threshold voltage shift (V/sub T/-shift) of the TFT under these conditions is negligible. The programming TFT in turn regulates the current of the drive TFT, and the pixel current therefore becomes independent of the threshold voltage of the drive TFT.     

Modeling of the reverse characteristics of a-Si:H TFTs

This paper investigates the reverse current-voltage (I-V) characteristics of inverted staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). Three mechanisms have been identified as the source of the reverse current: ohmic conduction, front channel conduction, and backchannel conduction. Ohmic conduction constitutes the physical limit for the reverse current and is due to the intrinsic conductivity of the a-Si:H and associated dielectric layers, which correlates with process integrity. The accumulation of holes and electrons at the front and back a-Si:H/a-SiN_x:H interfaces, respectively, forms the basis of the other two leakage mechanisms. The relative dominance of the one or the other mechanism depends on bias conditions, TFT geometry, and process conditions. This paper identifies these sources of leakage current and examines the effect of the critical geometrical parameters (such as channel length and overlap length) and bias conditions on these leakage components. Physical models to predict bias and geometry dependences are presented for a quantitative analysis of the leakage current. Modeling results corroborate experimental observations of leakage current extracted from a large number of TFTs that are put in parallel for improved measurement accuracy. The physical parameters of the model provide a method for estimation of the significant interface and bulk properties of the structure     

低温高速率沉积非晶硅薄膜及太阳电池

采用射频等离子体增强化学气相沉积(RF-PECVD)技术,保持沉积温度在125℃制备非晶硅薄膜材料及太阳电池。在85 Pa的低压下以及400～667 Pa的高压下,改变Si H4浓度和辉光功率等沉积参数,对本征a-Si材料的性能进行优化。结果表明,在高压下,合适的Si H4浓度和压力功率比可以使a-Si材料的光电特性得到优化,并且薄膜的沉积速率得到一定程度的提高。采用低压低速和高压高速的沉积条件,在125℃的低温条件下制备出效率为6.7%的单结a-Si电池,高压下本征层a-Si材料的沉积速率由0.06～0.08 nm/s提高到0.17～0.19 nm/s。