Asymptotic distributions for the performance analysis of hypothesistesting of isolated-point-penalization point processes

The performance of the likelihood ratio test is considered for a many-point interaction point process featuring a reduced number of isolated points. Limit theorems are proved that establish the Poissonian asymptotic distribution of the log-likelihood function for point processes with the isolated-point-penalization joint probability density function. The asymptotic distribution is used to approximate the detection probability associated with the likelihood ratio test. The approximation is compared to empirical results generated using Markov-chain Monte Carlo simulation. The reported results provide an efficient alternative method to simulation in assessing the performance of hypothesis testing for the point-process model considered     

Accurate computation of field reject ratio based on fault latency

It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated     

New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

Estimation of asynchronous circuit performances, such as speed, is one of the major reasons that still keeps that design style undeservedly unpopular. A simple logic simulator would be very useful in overcoming this problem if it is used for evaluating the worst-case delays in the paths of an asynchronous circuit using. In this paper a method for timing analysis of the asynchronous circuits using a VHDL simulator is presented. It is capable to deal with both non-sequential and sequential asynchronous circuit. An appropriate extension of the standard logic simulation process enables all worst-case delays for all paths in a digital circuit to be obtained with only one run of the simulation. High levels of accuracy are achieved using extensive gate modelling while statistical analysis of the results was also used to evaluate part of the parametric yield loss related to the delay. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.     

Test patterns reordering method based on Gamma distribution

Aiming at the problem that the test time is too long and the test efficiency is affected, an adaptive test patterns reordering method based on Gamma distribution was proposed. And a probability model based on Gamma distribution for the probability of each test pattern hitting fault was established. During the test, the circuit to be tested was added to the sample space, and the parameters of probability model were updated dynamically, and the test patterns were reordered synchronously. The experimental results showed that the reordered test patterns have higher test quality, which can reduce the test time and test cost of the faulty circuit. The algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process.     

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

Realizing a high measure of confidence for defect level analysis ofrandom testing [VLSI]

The defect level in circuit testing is the percentage of circuits, such as chips, which are defective and shipped for use after testing. In this work, it is demonstrated that the defect level of testing a circuit using random patterns should have a probability distribution rather than just a single value. Based on this concept, the confidence degree of a specified defect level for random testing can be derived, and the quality of circuit random testing is thus guaranteed. Results obtained based on random testing can be extended to other test methods, e.g., deterministic testing, pseudo-random testing, or functional testing. Experiments using computer simulation have been conducted for this work, and the results are very encouraging     

底充胶固化工艺对低k倒装焊器件可靠性的影响

利用四点弯曲实验测试了一组芯片(30片)的强度,使用威布尔统计模型描述了芯片失效率的分布,预测了在后续热循环过程中芯片的失效概率。通过有限元软件研究了底充胶固化工艺对芯片上方垂直开裂应力、焊点等效塑性应变及低k层最大等效应力的影响。结果表明:与未经固化的相比,底充胶固化工艺使得芯片的失效率从0.08%增大到0.37%,焊点的等效塑性应变增大约7倍,低k层的最大等效应力增大约18%。     

Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macro-modeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers (op-amps). The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.     

逆向统计模拟及在VLSI统计分析中的应用

本文在理论上提出了逆向统计模拟思想,并用以开发了NMOS数字集成电路统计模拟通用软件——STANMOS。应用该软件可定量得到工艺涨落及工艺干扰对电路性能的影响,分析电路性能的工艺灵敏度及成品率,确定主要影响电路性能一致性的工艺步骤。     

Use of test structures and results of electrical tests for silicon-on-sapphire integrated circuit processes

To obtain parametric data characterizing an IC processing schedule, a pattern of specialized test devices was used in conjunction with a powerful computer-controlled testing and data-reduction system. A test programming system which allows looping and branching was used to control instrumentation having capacitance measurement capability in addition to the usual voltage and current instrumentation. The test devices (MOS capacitor, transistor, and various other types) were tested automatically using the system. Computer-based data logging, analysis, and display generation techniques were necessary so the large bulk of data taken could be-reduced to physically meaningful parameters whose significance can be readily comprehended. In addition to the usual statistical analysis methods, a perspective three-dimensional plot showing parameter values as a function of position in the wafer plane was found most valuable. This data generation system is felt to be a necessary step to providing a complete characterization of both the capabilities and limitations of an IC fabrication scheme, which is vital to both the circuit designer and the line process engineer.     

Realistic non-destructive testing of integrated circuit bond wiring using 3-D X-ray tomography,reverse engineering,and finite element analysis

Within industries that manufacture and/or utilize semiconductor devices, integrated circuit (IC) bond wiring is tested for product assurance and counterfeit detection purposes through invasive and destructive probing. The examined unit is either partially damaged or fully destroyed during these tests and the uncertainties that existed prior to testing reappear when a new unit must replace the probed unit. Because packaged circuits serve such diverse roles in countless critical systems across many applications, there is a strong need for robust, quick, and non-destructive testing. As of now, methods to non-destructively test these components involve either simplified geometric modeling and finite element analyses, which make concessions to accuracy, or include more accurate forms of geometric acquisition but remain untested, unverified, and computationally expensive. The goals of this study are to test the validity of micro-CT as a tool to import accurate bond wire geometries to single- and multi-physical finite element testing and to produce a practical methodology for the image acquisition, processing, and simulation of integrated circuit bond wires with a focus on practicality and industrial applicability. A reverse engineering technique is examined as a valid simplification to the geometries retrieved from micro-CT. The reverse engineered geometry from micro-CT is then tested within a finite element simulation with the loading data gathered from a traditional destructive bond wire pull-test to examine its similarity. The results show that the proposed methodology can closely mirror the destructive test by highlighting the correct location of probable failure with the corresponding stress values in excess of the material's strength limits. In addition, the methodology reduces the finite element computational expense by a factor of four and produces a CAD editable model for geometric alteration or other finite element testing environments; similar to the files created by part manufacturers prior to production. The differences being that the model can include production process-related variations and can be utilized by an end-user seeking validation for a given application. The broader implications of this methodology include its application to iterative product design and extension to multi-physical, dynamic, and/or inordinately expensive testing conditions.     

A Modified Simulation-Based Multi-Signal Modeling for Electronic System

Multi-signal model is an effective modeling method applicable to large scale complex system. In this paper, an improved simulation-based modeling method for parametric fault is put forward. Two times of Monte-Carlo simulation are done in normal tolerance. Based on the estimated sample variance obtained from the first Monte-Carlo simulation, the analysis runs of the second Monte-Carlo is determined empirically to reduce the simulation cost. Then the statistical distribution of data from the second Monte-Carlo simulation is judged qualitatively by normality test. After that, an adaptive method is adopted to estimate the threshold range for signal feature in normal state, which can improve modeling precision. At last, the effectiveness of the proposed method is verified and the performances are compared to manifest the advantage of the proposed method. The work in this paper is valuable for future further research of complex system test and diagnosis based on multi-signal.     

A model of ultrasound backscatter for the assessment of myocardialtissue structure and architecture

A statistical parametric model of returning echoes from myocardium is theorized in order to investigate the relationship between normal myocardium structure and spectral signatures with the use of ultrasonic tissue characterization. It is hypothesized, that in a clinical setting the normal myofiber architecture in the left ventricular wall is structured as a matrix of cylindrical scatterers whose orientation and spatial distribution vary according to two different statistical distribution laws: (1) a Gaussian law to approximate parametric angular myofiber variability at each site within the myocardial wall; (2) a gamma distribution law to describe parametric regularity in scatterer interdistance. In the model, the effect of the angle of insonification with respect to the alignment of myofibers on ultrasound backscatter was considered. The slope of the power spectral density (PSD) evaluated within the echocardiographic transducer bandwidth has been used as a ultrasonic tissue characterization parameter. The model has been tested by computer simulation and in vitro measurements on myocardial pig tissue specimens. The concordance between experimental and simulated results confirms that the model accounts for the process underlying the echo formation from normal myocardium. Moreover, it provides a simple method of simulation which can be easily implemented and used for the assessment of pathologic alterations     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Fault Coverage Analysis of Peak-Detector Based BIST for RF LNAs

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865–870 MHz low noise amplifiers (LNAs), which constitute a mixed-signal circuit, a novel BIST method is developed. This BIST can be easily implemented with a RF peak detector and two comparators. The circuit used in the test and the LNA are designed using 0.35 μm CMOS technology. The simulation results show higher fault coverage than that of previous test methods. A total of twenty eight short and open (catastrophic) faults and eleven variation parameters have been introduced into the LNA, giving fault coverage of 100% for catastrophic faults and parametric variation. Thus, it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

A time-domain test for some types of nonlinearity

The bispectrum and third-order moment can be viewed as equivalent tools for testing for the presence of nonlinearity in stationary time series. This is because the bispectrum is the Fourier transform of the third-order moment. An advantage of the bispectrum is that its estimator comprises terms that are asymptotically independent at distinct bifrequencies under the hypothesis of linearity. An advantage of the third-order moment is that its values in any subset of joint lags can be used in the test, whereas when using the bispectrum the entire (or truncated) third-order moment is required to construct the Fourier transform. We propose a test for nonlinearity based upon the estimated third-order moment. We use the phase scrambling bootstrap method to give a nonparametric estimate of the variance of our test statistic under the hypothesis. Using a simulation study, we demonstrate that the test obtains its target significance level, with large power, when compared to an existing standard parametric test that uses the bispectrum. Further we show how the proposed test can be used to identify the source of nonlinearity due to interactions at specific frequencies. We also investigate implications for heuristic diagnosis of nonstationarity.     

基于伯努利分布的逻辑电路可靠度计算方法

在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.本文提出了一种利用概率统计模型计算逻辑电路可靠度的方法,将电路中的每个逻辑门是否正常输出看作一次随机事件,则发生故障的逻辑门数为某个特定值的概率服从伯努利分布;再利用实验统计单个逻辑门出错时电路的逻辑屏蔽特性,根据此方法计算出ISCAS'85和ISCAS'89基准电路可靠度的一个特定范围.理论分析和实验结果表明所提方法是准确和有效的.     

A quality measure for LSI components

Large-scale integration components are subjected to testing based on stuck fault modeling. Stuck fault testing often does not provide patterns for all possible stuck conditions that can exist in a circuit. Because of the incompleteness of test coverage, a new quality measure is needed-one that is not based on sample inspection. Such an LSI quality measure is described in this paper. The LSI quality measure can be related to component yield and is based on the stuck fault testing coverage, the physical circuit design layout, and the rate of faults occurring on elemental circuit geometries. The concept of the LSI quality measure is illustrated in this paper by an example. Starting from a block diagram and an assumed stuck fault coverage, some stuck faults are assumed to remain untested. For these untested faults, the elemental circuit geometries in a corresponding FET circuit layout are determined, and the quality measure calculated. Common sense rules are offered for optimizing the quality and lowering its cost impact on higher levels of assembly.