Polymer Field‐Effect Transistors Fabricated by the Sequential Gravure Printing of Polythiophene,Two Insulator Layers,and a Metal Ink Gate

The mass production technique of gravure contact printing is used to fabricate state‐of‐the art polymer field‐effect transistors (FETs). Using plastic substrates with prepatterned indium tin oxide source and drain contacts as required for display applications, four different layers are sequentially gravure‐printed: the semiconductor poly(3‐hexylthiophene‐2,5‐diyl) (P3HT), two insulator layers, and an Ag gate. A crosslinkable insulator and an Ag ink are developed which are both printable and highly robust. Printing in ambient and using this bottom‐contact/top‐gate geometry, an on/off ratio of >10⁴ and a mobility of 0.04 cm² V^?1 s^?1 are achieved. This rivals the best top‐gate polymer FETs fabricated with these materials. Printing using low concentration, low viscosity ink formulations, and different P3HT molecular weights is demonstrated. The printing speed of 40 m min^?1 on a flexible polymer substrate demonstrates that very high‐volume, reel‐to‐reel production of organic electronic devices is possible.     

Electrohydrodynamic Jet Printing Driven by a Triboelectric Nanogenerator

Electrohydrodynamic jet (e‐jet) printing is a high‐resolution printed electronics technique that uses an electric field to generate droplets. It has great application potential with the rapid development of flexible and wearable electronics. Triboelectric nanogenerators (TENG), which can convert mechanical motions into electricity, have found many high‐voltage applications with unique merits of portability, controllability, safety, and cost‐effectiveness. In this work, the application of a TENG is extended to printed electronics by employing it to drive e‐jet printing. A rotary freestanding TENG is applied as the high‐voltage power source for generating stable ink droplet ejection. The TENG‐driven droplet generation and ejection process and printed features with varied operation parameters are investigated. Results reveal that the jetting frequency could be controlled by the TENG's operation frequency, and high‐resolution printing with feature size smaller than nozzle size is achieved using the setup. Notably, TENG as the power source for e‐jet printing supplies a limited amount of current, which leads to better safety for both equipment and personnel compared to conventional high‐voltage power supplies. With the superiority of TENG in the sense of safety and cost, the work presents a promising solution for the next‐generation of high‐resolution printed electronics and broadens the scope of TENG application.     

Inkjet Printing of a Highly Loaded Palladium Ink for Integrated,Low‐Cost pH Sensors

An inkjet printing process for depositing palladium (Pd) thin films from a highly loaded ink (>14 wt%) is reported. The viscosity and surface tension of a Pd‐organic precursor solution is adjusted using toluene to form a printable and stable ink. A two‐step thermolysis process is developed to convert the printed ink to continuous and uniform Pd films with good adhesion to different substrates. Using only one printing pass, a low electrical resistivity of 2.6 μΩ m of the Pd film is obtained. To demonstrate the electrochemical pH sensing application, the surfaces of the printed Pd films are oxidized for ion‐to‐electron transduction and the underlying layer is left for electron conduction. Then, solid‐state reference electrodes are integrated beside the bifunctional Pd electrodes by inkjet printing. These potentiometric sensors have sensitivities of 60.6 ± 0.1 and 57 ± 0.6 mV pH^?1 on glass and polyimide substrates, and short response times of 11 and 6 s, respectively. Also, accurate pH values of real water samples are obtained by using the printed sensors with a low‐cost multimeter. These results indicate that the facile and cost‐effective inkjet printing and integration techniques may be applied in fabricating future electrochemical monitoring systems for environmental parameters and human health conditions.     

Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates

High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

Foldable All‐Solid‐State Supercapacitors Integrated with Photodetectors

Recent development in flexible electronics has promoted the increasing demand for their energy storage systems that will be lightweight, thin, flexible, and even foldable. Although various flexible supercapacitors recently have been successfully developed, the design and assembly of highly foldable supercapacitors have received less attention. Furthermore, foldable supercapacitors are in general operated independently with other electronics, resulting in some space and energy consumption from the external connection system. Therefore, the authors fabricate the foldable all‐solid‐state integrated devices with supercapacitor and photodetector functions in a simplified and compact configuration based on single‐walled carbon nanotube films and TiO₂ nanoparticles. The integrated devices not only retain the intrinsic capacitance behavior but also show excellent sensitivity of detecting white light. More importantly, the capacitance behavior of integrated devices remains almost unchanged and the photodetector behavior is quite stable even folded by 180° due to their unique integrated configuration. Such rational design of all‐solid‐state integrated devices will pave the way for assembling energy storage devices and other electronics into highly flexible and foldable integrated devices.     

Cover Picture: Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates (Adv. Funct. Mater. 18/2006)

Low‐voltage, hysteresis‐free, flexible thin‐film‐type electronic systems based on networks of single‐walled carbon nanotubes and bilayer organic–inorganic nanodielectrics are detailed in work by Rogers and co‐workers reported on p. 2355. The cover image shows a schematic array of such thin‐film transistors (TFTs) on a plastic substrate. The structure of the bilayer nanodielectric, which consists of a film of HfO₂ formed by atomic layer deposition and an ultrathin layer of epoxy formed by spin‐casting, is also illustrated schematically. High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

Single‐Crystal Organic Nanowire Electronics by Direct Printing from Molecular Solutions

A one‐step process to generate single‐crystal organic nanowire arrays using a direct printing method (liquid‐bridge‐mediated nanotransfer molding) that enables the simultaneous synthesis, alignment, and patterning of nanowires from molecular ink solutions is reported. Using this method, many single‐crystal organic nanowires can easily be synthesized by self‐assembly and crystallization of organic molecules within the nanoscale channels of molds, and these nanowires can then be directly transferred to specific positions on substrates to generate nanowire arrays by a direct printing process. The position of the nanowires on complex structures is easy to adjust, because the mold is movable on the substrates before the polar liquid layer, which acts as an adhesive lubricant, is dried. Repeated application of the direct printing process can be used to produce organic nanowire‐integrated electronics with two‐ or three‐dimensional complex structures on large‐area flexible substrates. This efficient manufacturing method is used to fabricate high‐performance organic nanowire field‐effect transistors that are integrated into device arrays, inverters, and phototransistors on flexible plastic substrates.     

Programmable logic circuits for functional integrated smart plastic systems

In this paper, we present a functional integrated plastic system. We have fabricated arrays of organic thin-film transistors (OTFTs) and printed electronic components driving an electrophoretic ink display up to 70 mm by 70 mm on a single flexible transparent plastic foil. Transistor arrays were quickly and reliably configured for different logic functions by an additional process step of inkjet printing conductive silver wires and poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) resistors between transistors or between logic blocks. Among the circuit functions and features demonstrated on the arrays are a 7-stage ring oscillator, a D-type flip-flop memory element, a 2:4 demultiplexer, a programmable array logic device (PAL), and printed wires and resistors. Touch input sensors were also printed, thus only external batteries were required for a complete electronic subsystem. The PAL featured 8 inputs, 8 outputs, 32 product terms, and had 1260 p-type polymer transistors in a 3-metal process using diode-load logic. To the best of our knowledge, this is the first time that a PAL concept with organic transistors has been demonstrated, and also the first time that organic transistors have been used as the control logic for a flexible display which have both been integrated on to a single plastic substrate. The versatility afforded by the additive inkjet printing process is well suited to organic programmable logic on plastic substrates, in effect, making flexible organic electronics more flexible.     

Water‐Based Isotropically Conductive Adhesives: Towards Green and Low‐Cost Flexible Electronics

This paper reports the first high‐performance water‐based isotropically conductive adhesives (WBICAs) – a promising material for both electrical interconnects and printed circuits for ultralow‐cost flexible/foldable printed electronics. Through combining surface iodination and in situ reduction treatment, the electrically conductivity of the WBICAs are dramatically improved (8 × 10^‐5 Ω cm with 80 wt% of silver); moreover, their reliability (stable for at least 1440 h during 85 °C/85% RH aging) meets the essential requirements for microelectronic applications. Prototyped applications in carrying light emitting diode (LED) arrays and radio frequency identification (RFID) antennas on flexible substrates were demonstrated, which showed satisfactory performances. Moreover, their water‐based character may render them more environmentally benign (no volatile organic chemicals involved in the printing and machine maintenance processes), more convenient in processing (reducing the processing steps), and energy economic (thermally sintering the silver fillers and curing the resin is not necessary unlike conventional ICAs). Therefore, they are especially advantageous for mass‐fabricating flexible electronic devices when coupled with paper and other low‐cost substrate materials such as PET, PI, wood, rubber, and textiles.     

All‐Printed Flexible and Stretchable Electronics with Pressing or Freezing Activatable Liquid‐Metal–Silicone Inks

Liquid‐metal (LM)‐based flexible and stretchable electronics have attracted widespread interest in wearable computing, human–machine interaction, and soft robotics. However, many current examples are one‐off prototypes, whereas future implementation requires mass production. To address this critical challenge, an integrated multimaterial 3D printing process composed of direct ink writing (DIW) of sealing silicone elastomer and special LM‐silicone (LMS) inks for manufacturing high‐performance LM‐based flexible and stretchable electronics is presented. The LMS ink is a concentrated mixture of LM microdroplets and silicone elastomer and exhibits excellent printability for DIW printing. Guided by a verified theoretical model, a printing process with high resolution and high speed can be easily implemented. Although LMS is not initially conductive, it can be activated by pressing or freezing. Activated LMS possesses good conductivity and significant electrical response to strain. Owing to LMS's unique structure, LMS‐embedded flexible electronics exhibit great damage mitigation, in that no leaking occurs even when damaged. To demonstrate the flexibility of this process in fabricating LM‐based flexible electronics, multilayer soft circuits, strain sensors, and data gloves are printed and investigated. Notably, utilizing LMS's unique activating property, some functional circuits such as one‐time pressing/freezing‐on switch can be printed without any structural design.     

Room‐Temperature Printing of Organic Thin‐Film Transistors with π‐Junction Gold Nanoparticles

Printing semiconductor devices under ambient atmospheric conditions is a promising method for the large‐area, low‐cost fabrication of flexible electronic products. However, processes conducted at temperatures greater than 150 °C are typically used for printed electronics, which prevents the use of common flexible substrates because of the distortion caused by heat. The present report describes a method for the room‐temperature printing of electronics, which allows thin‐film electronic devices to be printed at room temperature without the application of heat. The development of π‐junction gold nanoparticles as the electrode material permits the room‐temperature deposition of a conductive metal layer. Room‐temperature patterning methods are also developed for the Au ink electrodes and an active organic semiconductor layer, which enables the fabrication of organic thin‐film transistors through room‐temperature printing. The transistor devices printed at room temperature exhibit average field‐effect mobilities of 7.9 and 2.5 cm² V^?1 s^?1 on plastic and paper substrates, respectively. These results suggest that this fabrication method is very promising as a core technology for low‐cost and high‐performance printed electronics.     

Sources of Hysteresis in Carbon Nanotube Field‐Effect Transistors and Their Elimination Via Methylsiloxane Encapsulants and Optimized Growth Procedures

The origins of gate‐induced hysteresis in carbon nanotube field‐effect transistors are explained and techniques to eliminate this hysteresis with encapsulating layers of methylsiloxane and modified processes for nanotube growth are reported. A combined experimental and theoretical analysis of the dependence of hysteresis on the gate voltage sweep‐rate reveals the locations, types, and densities of defects that contribute to hysteresis. Devices with designs that eliminate these defects exhibit more than ten times reduction in hysteresis compared to conventional layouts. Demonstrations in individual transistors that use both networks and arrays of nanotubes, and in simple logic gates built with these devices, illustrate the utility of the proposed approaches.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

Non‐Volatile Organic Memory Elements Based on Carbon‐Nanotube‐Enabled Vertical Field‐Effect Transistors

High‐performance non‐volatile memory elements based on carbon‐nanotube‐enabled vertical field‐effect transistors (CN‐VFETs) are demonstrated. A thin crosslinking polymer layer, benzocyclobutene (BCB), on top of the gate dielectric acts as the charge storage layer. This results in a large, fully gate sweep programmable, hysteresis in the cyclic transfer curves exhibiting on/off ratios >4 orders of magnitude. The carbon nanotube random network source electrode facilitates charge injection into the charge storage layer, realizing the strong memory effect without sacrificing mobility in the vertical channel. Given their intrinsically simple fabrication and compact size CN‐VFETs could provide a path to cost‐effective, high‐density organic memory devices.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

Printed Sub‐2 V Gel‐Electrolyte‐Gated Polymer Transistors and Circuits

The fabrication and characterization of printed ion‐gel‐gated poly(3‐hexylthiophene) (P3HT) transistors and integrated circuits is reported, with emphasis on demonstrating both function and performance at supply voltages below 2 V. The key to achieving fast sub‐2 V operation is an unusual gel electrolyte based on an ionic liquid and a gelating block copolymer. This gel electrolyte serves as the gate dielectric and has both a short polarization response time (<1 ms) and a large specific capacitance (>10 µF cm^?2), which leads simultaneously to high output conductance (>2 mS mm^?1), low threshold voltage (<1 V) and high inverter switching frequencies (1–10 kHz). Aerosol‐jet‐printed inverters, ring oscillators, NAND gates, and flip‐flop circuits are demonstrated. The five‐stage ring oscillator operates at frequencies up to 150 Hz, corresponding to a propagation delay of 0.7 ms per stage. These printed gel electrolyte gated circuits compare favorably with other reported printed circuits that often require much larger operating voltages. Materials factors influencing the performance of the devices are discussed.     

Carbon nanotubes vacuum field emission differential amplifier integrated circuits

A novel vacuum field emission differential amplifier integrated circuit (VFE diff-amp IC) utilising carbon nanotube (CNT) emitters is presented. A dual-mask microfabrication process is employed to achieve the VFE diff-amp IC by integrating identical CNT VFE transistors with built-in split gates and anodes. The pair of integrated amplifiers shows low gate turn-on voltage, large DC gain, a reasonable transconductance, and a good common-mode rejection ratio. The approach demonstrates a new way for development of temperature- and radiation-tolerant VFE integrated microelectronics.     

喷墨印制PCB用新型纳米银导电油墨的研发现状及趋势

喷墨打印加成法制造电路板,可明显改善传统减成法效率低、成本高、污染重等缺点,因而受到业内广泛关注。该方法所使用的新型功能材料纳米银导电油墨,因具有烧结温度低、导电性能好等优点,近年来成为全球电子油墨行业的研发热点之一。文章详细介绍了纳米银油墨在印制电子产品电路制作领域的应用,并对喷印纳米金属油墨的技术要求、纳米银油墨的特点及主要不足进行了评述,重点展示了全球纳米银油墨的产品开发动态,同时对新型喷印纳米金属油墨的制备与研发提出了一些建议。     

Capacitively Coupled Hybrid Ion Gel and Carbon Nanotube Thin‐Film Transistors for Low Voltage Flexible Logic Circuits

The lamination of a high‐capacitance ion gel dielectric layer onto semiconducting carbon nanotube (CNT) thin‐film transistors (TFTs) that are bottom‐gated with a low‐capacitance polymer dielectric layer drastically reduces the operating voltage of the devices resulting from the capacitive coupling effect between the two dielectric layers sandwiching the CNT channel. As the CNT channel has a network structure, only a compact area of ion gel is required to make the capacitive coupling effect viable, unlike the planar channels of previously reported transistors that required a substantially larger area of ion gel dielectric layer to induce the coupling effect. The capacitively coupled CNT TFTs possess superlative electrical characteristics such as high carrier mobilities (42.0 cm² (Vs)^?1 for holes and 59.1 cm² (Vs)^?1 for electrons), steep subthreshold swings (160 mV dec^?1 for holes and 100 mV dec^?1 for electrons), and low gate leakage currents (<1 nA). These devices can be further integrated to form complex logic circuits on flexible substrates with high mechanical resilience. The layered geometry of the device coupled with scalable solution‐based fabrication has significant potential for large‐scale flexible electronics.