Designing Dynamic Carry Skip Adders: Analysis and Comparison

Addition represents an important operation that significantly impacts the performance of almost every data processing system. Due to their importance and popularity, addition algorithms and their corresponding circuit implementations have consistently received attention in research circles, over the years. One of the most popular implementations for long adders is the carry skip adder. In this paper, we present the design space exploration for a variety of carry skip adder implementations. More specifically, the paper focuses on the implementation of these adders using traditional as well as novel dynamic circuit design styles. 8–16–32–64-bit adders were implemented using traditional domino, footless domino, and data driven dynamic logic (D3L) in ST Microelectronics 45 nm 1 V CMOS process. In order to further exploit the advantages of the domino and D3L approaches, a new hybrid methodology combining both strategies was implemented and presented in this work. The adders were analyzed for energy-delay trade-offs at different process corners. They were also examined for their sensitivity to process and supply voltage variations. Comparative simulation results reveal that the full D3L adder ensures a better energy-delay product over all process corners (down to 34 % and 25 % lower than the domino and hybrid implementations, respectively, at the typical corner), while showing at the same time similar performance in terms of process and supply voltage variability as compared to the other considered carry skip adder configurations.     

基于计数器实现的加法器自测试

文章研究了行波进位加法器和先行进位加法器的测试向量生成，并基于计数器实现了这两种加法器的自测试。实验结果表明，所得的测试向量针对不同的目标工艺均可以实现被测加法器的100％故障覆盖率，且测试向量生成电路易扩展，能够实现测试复用。     

Minimal Energy Path Planning for Wireless Robots

In this paper, the problem of optimizing energy for communication and motion is investigated. We consider a single mobile robot with continuous high bandwidth wireless communication, e.g. caused by a multimedia application like video surveillance. This robot is connected to radio base station(s), and moves with constant speed from a given starting point on the plane to a target point. The task is to find the best path such that the energy consumption for mobility and the communication is optimized. This is motivated by the fact that the energy consumption of radio devices increases polynomially (at least to the power of two) with the transmission distance. We introduce efficient approximation algorithms to find the optimal path given the starting point, the target point and the position of the radio stations. We exemplify the influence of the communication cost by a starting scenario with one radio station. We study the performance of the proposed algorithm in simulation, compare it with the scenario without applying our approach, and present the results.

音乐的多轨分期录音及动态处理

在音乐的立体声多轨录音中,大致有两种录音方式:同期录音和分期录音。同期录音是在同一时间里,对音乐的各个声部进行一次性的录音;分期录音就是在不同的时间里,对所有的音乐组成(器乐演奏、声乐演唱)进行多次性的录音。动态处理就是利用压缩/限幅器、噪声门和嘶声消除器等动态处理设备对声音信号电平进行控制。无论是广播节目制作、电影或是电视录音等有关的工作,都需要进行各种各样的动态处理。本文主要介绍音乐的立体声多轨分期录音的程序和方法,以及音乐制作中独唱、合唱声部,电声乐器声部,打击乐声部的动态处理技巧。1音乐的多轨分期录…     

On Built-In Self-Test for Adders

We evaluate some of the previously proposed test approaches for various types of adders in an attempt to find an architecture-independent algorithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self-Test (BIST) approach provides the highest fault coverage for most types of adders and, equally important, it is simple to implement.     

Designing High-Speed Adders in Power-Constrained Environments

Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage is typically obtained at the expense of speed performances. This paper presents a novel technique to realize D3L parallel prefix tree adders without significantly compromising speed performance. When applied to a 64-bit Kogge–Stone adder realized with 90-nm complementary metal–oxide–semiconductor (CMOS) technology, the proposed technique leads to an energy-delay product that is 29% and 21% lower than its standard domino logic and conventional D3L counterparts, respectively. It also shows a worst case delay that is 10% lower than that of the D3L approach and only 5% higher than that of the conventional domino logic.      

Easily Testable Cellular Carry Lookahead Adders

Cellular Carry Lookahead (CLA) adders are systematically implemented in arithmetic units due to their regular, well-balanced structure. In terms of testability and with respect to the classical Cell Fault Model (CFM), cellular CLA adders have poor testability by construction. Design-for-testability (DFT) modifications for cellular CLA adders have been proposed in the literature providing complete CFM testability making the adders either level-testable or C-testable. These designs impose significant area and performance overheads. In this paper, we propose DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance. Complete CFM testability is achieved without adding any extra inputs to the adder, with very small area and performance overheads, thus providing a practical solution. The proposed DFT scheme requires only 1 extra output and it is not necessary to put the circuit in a special test mode, while the earlier schemes require the addition of 2 extra inputs to set the circuit in test mode. A rigorous proof of the linear-testability of the adder is given and a sufficient linear-sized test set is provided that guarantees 100% CFM fault coverage. Surprisingly, the size of the proposed linear-sized test set is, in most practical cases, comparable or even smaller than a logarithmic-sized test set proposed in the literature.     

感应电机能量最优化控制的研究

感应电机能量优化控制常根据电机静态模型采用恒转差频率控制。但该控制方案会导致调速系统的动态性能和稳定性降低。从感应电机的动态模型出发,提出了一种借助转子磁链控制实现感应电机能量优化的控制方案。根据外环给定电磁转矩的不同,调整内环转子磁链给定值,以达到能量优化控制的目的。在调速过程中,控制方案确保转子磁链紧跟给定值,使输出的电磁转矩紧跟给定值。因此,系统的稳定性、动态性能良好。     

动态正交的跳频异步组网性能分析

针对跳频同步组网抗阻塞干扰能力差和跳频异步组网效率低的现状,提出了一种跳 频频率表动态正交的异步组网方式。结合设置宽间隔跳频频率表,使得组网效率接近于同步 组网的效率,同时抗阻塞干扰能力优于同步组网。该组网方式可以更好地发挥跳频通信装备 的作战效能。     

Binary Adders on Quantum-Dot Cellular Automata

This article describes the design of adder units on quantum-dot cellular automata (QCA) nanotechnology, which promises very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct pipelined structures without the earlier noise problems, avoided by careful clocking organization, and the modular layouts are verified with the QCADesigner coherence vector simulation. Our designs occupy only a fraction of area compared to the previous noise rejecting design, while having also superior performance, and it is shown that the wiring overhead of the arithmetic circuits on QCA grows with square-law dependence on the operand word length. Power analysis at the fundamental Landauer’s limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the clock rates of the adder units on molecular QCA are only tens of gigahertz, while the switching speed of the technology is in the terahertz regime.     

三相异步电机的节能探讨

从分析三相异步电动机产生损耗的原因出发,通过案例的详细分析,介绍了三相异步电动机常用的节能技术与方法。     

三相异步电动机智能节能控制器的研究

异步电机在工农业生产中应用非常广泛。在电机起动时，会产生较大的电流，对系统本身以及电网都会产生较大的影响，并造成了电能的浪费。当电机的负载低于额定负载的75%时，效率较低，造成了能源浪费。经过理论分析，设计了一种电机智能节能控制器，用于电机的节能、软起动和运行保护。     

基于幂表的并行加法器的归纳验证

介绍了基于幂表和重写规则的并行加法器的功能描述,直接使用重写归纳证明技术验证了这些描述的正确性,为重写技术用于描述和验证更加复杂的硬件电路奠定了基础.     

动态分层异步教学方法研究与实践

针对传统的同步教学模式忽视学生个性和差异性,制约学生学习主动性和自觉性的问题,本文进行了动态分层异步教学方法研究与实践。这种研究性教学方法遵循因材施教原则组织教学,使教学动态分层化。我们构建了异步教学结构,实现了学生学习自主化与教师指导异步化。实践表明,这种教学模式可以促进学生创新能力的提高。     

一种超前进位加法器的新颖BIST架构

针对超前时进位加法器（CLA），提出了一种高效的BIST架构。这种新的架构结合了确定性测试和伪随机测试的优点，并避免了各自的短处。同时，还提出了一个测试向量集，并充分利用了CLA加法器内部结构的规整性，向量集规模较小，便于片内集成。最后，提出了一种计算特征值的新方法。     

An Asymmetric and Asynchronous Energy Conservation Protocol for Vehicular Networks

Intelligent Transportation Systems (ITS) improve passenger/pedestrian safety and transportation productivity through the use of vehicle-to-vehicle and vehicle-to-roadside wireless communication technologies. Communication protocols in these environments must meet strict delay requirements due to the high moving speed of the vehicles. In this paper, we propose an energy-conservative MAC layer protocol, named DSRC-AA, based on IEEE 802.11 that provides power saving to the ITS communication modules (e.g., On Board Units, portable devices, and Road Side Units) while ensuring the bounded delay. DSRC-AA, a generalization of the Asynchronous Quorum-based Power-Saving (AQPS) protocols, capitalizes on the clustering nature of moving vehicles and assigns different wake-up/sleep schedules to the clusterhead and the members of a cluster. DSRC-AA is able to dynamically adapt the schedules to meet the communication delay requirements at various vehicle moving speed. Simulation results show that DSRC-AA is able to yield more than 44 percent reduction in average energy consumption as compared with the existing AQPS protocols, if to be used in vehicular networks.     

一种采用较少加法器的FIR滤波器实现方法

该文提出的无乘法器结构的滤波器实现方法主要基于移位相加操作、子表达式和乘法器模块的思想。首先提出部分共同子表达式概念,然后引入矩阵分析法寻找合适的部分共同子表达式,尽可能减少加法器数目。通过比较可以看出,采用这种结构的滤波器实现方法比一般方法大大节省硬件资源。另外,该文对所提出的用部分共同子表达式减少加法器数目的方法进行了理论分析,结果表明这种方法尤其适合于抽头系数较多的情况,可以大大减少搜索运算量。     

The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style

A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are asynchronous, these pipelines avoid problems related to high-speed clock distribution, such as clock power, management of clock skew, and inflexibility in handling varied environments. The designs are based on the well-known PSO style of Williams and Horowitz as a starting point, but achieve significant improvements through novel protocol optimizations: the pipeline communication is structured so that critical events can be detected and exploited earlier. A special focus of this work is to target extremely fine-grain or gate-level pipelines, where the datapath is sectioned into stages, each consisting of logic that is only a single level deep. Both dual-rail and single-rail pipeline implementations are proposed. All the implementations are characterized by low-cost control structures and the avoidance of explicit latches. Post-layout SPICE simulations, in 0.18-mum technology, indicate that the best dual-rail LP design has more than twice the throughput (1.04 giga data items/s) of Williams' PSO design, while the best single-rail LP design achieves even higher throughput (1.55 giga data items/s).     

MECOR: Minimal Energy Consumption with Optimized Routing in MANET

Energy and routing efficiency is a long-research topic from past decades in the area of MANET. The prior research contribution focusing on addressing both the issues are associated with issues like (1) few benchmarked studies, (2) adoption of conventional routing protocols based on shortest path to mitigate both issues, and (3) inefficient design principles of routing. Hence, this paper proposes a novel routing protocol in mobile ad hoc network (MANET) termed as MECOR i.e. minimal energy consumption with optimized routing. MECOR presents a simple communication strategy based on mathematical and signaling properties of mobile nodes in MANET to jointly address the energy and routing issues in MANET. The outcome of the MECOR was compared with conventional routing algorithm as well as recent studies of energy efficient routing policy to find that MECOR can minimize 58.82 % of energy in most challenging mobility scenarios of MANET.     

The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style

This paper introduces a high-throughput asynchronous pipeline style, called high-capacity (HC) pipelines, targeted to datapaths that use dynamic logic. This approach includes a novel highly-concurrent handshake protocol, with fewer synchronization points between neighboring pipeline stages than almost all existing asynchronous dynamic pipelining approaches. Furthermore, the dynamic pipelines provide 100% buffering capacity, without explicit latches, by means of separate pullup and pulldown control for each pipeline stage: neighboring stages can store distinct data items, unlike almost all existing latchless dynamic asynchronous pipelines. As a result, very high throughput is obtained. Fabricated first-input-first-output (FIFO) designs, in 0.18-m technology, were fully functional over a wide range of supply voltages (1.2 to over 2.5 V), exhibiting a corresponding range of throughputs from 1.0-2.4 giga items/s. In addition, an experimental finite-impulse response (FIR) filter chip was designed and fabricated with IBM Research, whose speed-critical core used an HC pipeline. The HC pipeline exhibited throughputs up to 1.8 giga items/s, and the overall filter achieved 1.32 giga items/s, thus obtaining 15% higher throughput and 50% lower latency than the fastest previously-reported synchronous FIR filter, also designed at IBM Research.