Determination of contact parameters of interconnecting layers in VLSI circuits

This paper presents a generalized electrical model of the interlayer contacts in integrated circuits and discusses various test structures capable of providing experimental data on the contacts. The techniques used for obtaining the specific contact resistance for the contacts and, where appropriate, the modification to conducting layer resistivities due to interactions Within the contact area are outlined. Using one of the techniques, experimental data on a polysilicon to single-crystal silicon contact is used as an example to obtain contact information. These results are discussed along with the experimental limitations applicable to the various techniques.     

异质结n+多晶硅/n型4H-SiC欧姆接触的制备

从理论和实验的角度研究了n型4H-SiC上的多晶硅欧姆接触.在P型4H-SiC外延层上使用P+离子注入来形成TLM结构的n阱.使用LPCVD淀积多晶硅并通过P+离子注入及扩散进行掺杂,得到的多晶硅方块电阻为22Ω/□.得到的n+多晶硅/n-SiC欧姆接触的比接触电阻为3.82×10-5Ω·cm2,接触下的注入层的方块电阻为4.9kΩ/□.对n+多晶硅/n-SiC欧姆接触形成的机理进行了讨论.     

A direct measurement of interfacial contact resistance

A method is described for directly measuring interfacial contact resistance and estimating the degree of uniformity of the interfacial layer in metal-semiconductor contacts. A two-dimensional resistor network model is used to obtain a relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a homogeneous interfacial layer. Measurement results are given for 98.5% Al/1.5% Si and 100 % Al contacts on n-type silicon.     

MCM-D技术电热特性综述

本文主要说明了淀积型多芯片组件(MCM-D)技术所使用的主要材料的热特性。此技术采用倒装片技术把硅芯片安装到硅基板上。阐述了薄膜电阻和接触电阻的测量与所使用金属的温度范围-28℃-100℃的比较。一套典型的试验结构诸如开尔文接触、横桥电阻(CBR)及Van der Pauw 结构不仅已用于此技术,而且为了测试通过球倒装片连接的接触电阻,采用一新的开尔文式结构。已获得MCM封装的热模型,并考虑由此类封装增加的所有的热电阻。     

反应生成的TiSi_2薄膜特性及TiSi_2/poly Si栅结构特性、TiSi_2/n~+-Si接触特性和形貌的研究

<正> 一、引言 随着集成电路的发展,集成度的提高,器件尺寸将逐渐缩小,此时RC延迟时间及接触电阻的影响将越来越显著。目前广泛应用的多晶硅栅材料在亚微米技术中已不再适用,取代它的有硅化物/多晶硅栅。由于TiSi_2的电阻率低,形成温度低,因此是人们最重视的硅化物。本文对反应生成的TiSi_2/poly Si栅结构及TiSi_2/n~+-Si的接触特性进行了系统研究,有助于     

Experimental study of the minority-carrier transport at the polysilicon—monosilicon interface

This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties Were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate, the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n⁺polysilicon-n⁺monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 10⁴cm/s.     

Titanium silicide/silicon nonohmic contact resistance for NFET's,PFET's, diffused resistors, and NPN's in a BiCMOS technology

Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the body of diffused resistors, and into the active region of NPN's through the titanium silicide/silicon interface. This contact resistance can represent a significant fraction of the total device resistance for devices of small dimensions, and contributes to a loss in circuit performance. The impedance of this interface is a function of the doping level in the silicon immediately below the interface, and this doping level is a sensitive function of the heat applied to the structure after the formation of the silicide. The correspondence of FET series resistance, emitter resistance, the diffused resistor end effects and the non-ohmic nature of a contact after heat is applied is presented. Use of a rapid thermal anneal to obtain the requisite silicide characteristics while minimizing the impact on the contact resistance is demonstrated for a 0.8-μm BiCMOS technology     

Direct measurements of interfacial contact resistance, end contact resistance, and interfacial contact layer uniformity

A four-terminal microelectronic test structure and test method are described for electrically determining the degree of uniformity of the interfacial layer in metal-semiconductor contacts and for directly measuring the interfacial contact resistance. A two-dimensional resistor network model is used to obtain the relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a uniform interfacial layer. A new six-terminal test structure is used for the direct measurement of end contact resistance and the subsequent determination of front contact resistance. A methodology is described for reducing the effects of both contact-window mask misalignment and parasitic resistance associated with these measurements. Measurement results are given for 98.5-percent Al/1.5- percent Si and 100-percent Al contacts on n-type silicon.     

Observation of high interface state densities at the silicon/oxide interface for low doped polysilicon/oxide/silicon capacitor structures

In this work, we present new observations noted in the capacitance–voltage behaviour of polysilicon/oxide/silicon capacitor structures. As the active doping concentration reduces in the polysilicon layer, an anomalous capacitance–voltage behaviour is measured which is not related directly to depletion into the polysilicon gate. From examination of the frequency dependence of the capacitance–voltage characteristic, in conjunction with analysis and simulation, the anomalous capacitance–voltage behaviour is explained by the presence of a high density of near-monoenergetic interface states located at the silicon/oxide surface. The density and energy level of the interface states are determined. Furthermore, the work presents a mechanism by which the polysilicon doping level can impact on the properties of the silicon/oxide interface.     

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.     

Correlation between the diffusive and electrical barrier properties of the interface in polysilicon contacted n+-p junctions

The diffusion of As from polysilicon into boron-implanted single-crystal silicon through different interfaces obtained with different surface preparation techniques prior to polysilicon deposition is studied. The impurity profiles have been analyzed by SIMS andC-Vmeasurements and ESCA has been used to determine the structural properties of the interface. Electrical measurements on diodes have been performed to study the diode characteristics and the electrical interface resistance. The diffusion through chemically grown oxide layers is found to be strongly retarded with respect to "oxygen-free" interfaces. A strong correlation appears to exist between the diffusive and electrical barrier properties of such interfaces. For increasing oxygen content at the interface, the minimum diffusion cycle required to obtain good diode ideality factors is higher as is the electrical interface resistance. We have observed an order of magnitude increase in the contact resistance for annealing temperatures between 800° and 900°C. One of the major conclusions is that the necessity to go to higher temperatures to decrease the series resistance of the polysilicon contacts in the case of chemically grown interface oxides is compromising their use in high-performance VLSI technologies.     

Three-dimensional base distributed effects of long stripe BJT's: ACeffects on input characteristics

The small-signal voltage and current distributed effects in the polysilicon and intrinsic base regions of long stripe bipolar junction transistors (BJT's) at high frequencies are investigated, and simple analytic equations describing the voltage and current distribution in these regions are derived. It is shown that the frequency-dependent debiasing effects in the polysilicon contacts and intrinsic base region change the current behavior and modulate the input admittance. The current and voltage distributions in the polysilicon region are nonuniform and vary with frequency. Conventional two-dimensional (2-D) device simulations cannot accurately predict this three-dimensional (3-D) effect. A quasi-3D simulation scheme combining a 2-D device simulator and the distributed model is presented to properly and efficiently describe the input characteristics of the device at high frequencies. It is also shown the use of various polysilicon sheet resistances, geometry sizes, and layout structures changes the distributed characteristics and modulates device performance at high frequencies. The impact of the layout structure and geometry size on RF circuit design due to the distributed effects is also studied     

Impact of silicide formation on the resistance of commonsource/drain region

Silicide had been used to reduce the sheet resistance of diffusion region for almost 20 years. However, as the silicided region becomes small, the contact resistance of silicide/silicon interface becomes higher than the resistance of the Si diffusion region such that current may not flow into the silicide layer. The effect of silicide thickness and contact resistivity on the total resistance of the silicided diffusion region was studied by two-dimensional simulation. It is observed that below a threshold length, the resistance of silicided diffusion region is higher than the unsilicided diffusion region if the silicon consumption during silicide formation is taken into consideration. Thinner silicide and lower contact resistivity reduce total resistance and threshold length but the threshold length is still much longer than the typical design rule of poly-Si to poly-Si distance. It is thus recommended to inhibit silicide formation at the common source/drain region at the metal-gate generation     

Effect of emitter contact materials on high-performance verticalp-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements     

Extensive electrical and thermal characterization of an MCM-Dtechnology

In this paper, it is shown the work carried out on thermal characterization of the main materials employed in the deposited-type multichip module (MCM-D) technology. In this technology, silicon chips are mounted onto a silicon substrate by a flipchip technique. The substrates can be either passive with interconnection lines, Rs, Cs, and Ls or active with complementary metal oxide semiconductor (CMOS) technology cells. The metals used in this technology are aluminum for interconnection purposes, tantalum silicide for making resistors and a multilayer of wettable metal for solder connection. Measurements of sheet resistance and contact resistance versus temperature in the range of -28°C to 100°C of the metals used in the technology are shown. A set of classic test structures such as Kelvin contacts, cross bridge resistors (CBR), and Van der Pauw structures have been used for this purpose as well as a new Kelvin-like structure to test the contact resistance of the Flip Chip connection through the ball. This structure has been proven to be very sensitive allowing the measurement of changes in ball resistance in the range of mΩ. A thermal model of the MCM package has been obtained, taking into account all the thermal resistances added by this kind of package     

A transfer length model for contact resistance of two-layer systemswith arbitrary interlayer coupling under the contacts

An improved analytical solution to the two-layer transmission line model for determining contact resistances to semiconductor layers is presented. In contrast to previously published two-layered analyses, the present solution is valid for arbitrary strength linear coupling between the two conducting layers in the region under the contact. A comparison of limiting cases and a physical interpretation of the differences between predictions of this model and previous models are presented. The predicted resistance versus pad separation behaviour obtained from the present model and from a two-layer model which assumed weak interlayer coupling beneath the contacts are compared for identical physical structures. Experimental data for contact resistance measurements on a double-barrier resonant tunneling diode structure are presented. The measured data exhibit the nonlinear resistance versus pad spacing predicted by the model and show a dependence on current level which can be modelled as a variation of the interlayer coupling strength. The values of the contact resistance, interlayer coupling resistance and sheet resistance extracted from the measured data using the present model and the weakly coupled model are presented and compared with independently measured and calculated parameters     

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

The effect of thin interfacial oxides on the electrical characteristics of silicon bipolar devices

The effect of thin interfacial oxides on the impurity diffusion from polysilicon to the silicon substrate has been studied in detail. Polysilicon films were deposited on the silicon substrate in two different process conditions to control the thickness of interfacial oxides. Results show that the presence of about 1-nm-thick oxides retarded the impurity diffusion by about 10 nm and an increase of the sheet resistance of about 10 percent has been observed. Bipolar devices, which are sensitive to the impurity profiles, were fabricated with identical processing apart from the polysilicon deposition conditions. A detailed analysis of their electrical characteristics shows the difference of collector current components and hence the increase of current gain by about two times. These results indicate that the effect of interfacial oxides on the impurity profile is expressed by the segregation coefficientm, which is the ratio of Csi/CpolySiat the interface. The sensitivity ofmfor the device characteristics was calculated by a process-device simulator, and it is demonstrated that the current gain is a strong function ofmfor shallow emitters.     

The split-cross-bridge resistor for measuring the sheet resistance, linewidth, and line spacing of conducting layers

A new test structure was developed for evaluating the line spacing between conductors on the same layer by using an electrical measurement technique. This compact structure can also be used to measure the sheet resistance, linewidth, and line pitch of the conducting layer. Using an integrated-circuit fabrication process, this structure was fabricated in diffused polycrystalline silicon and metal layers. These structures were measured optically and electrically, and these measured value were compared. For the techniques used, the optical measurements were typically one-quarter micrometer greater than the electrical measurements for the polysilicon and metal layers. Most electrically measured line pitch values were within 2 percent of the designed value. A small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values. Test results confirm the structure's self-checking feature based on the line pitch. That is, a small difference between the measured and designed line pitch is used to validate sheet resistance, linewidth, and line spacing values. Rules for designing the test structure are presented in detail.