Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors     

Optically variable micro-mirror arrays fabricated by graytone lithography

The fabrication of micro-mirror based portrait and non-portrait images has been demonstrated by graytone lithography. The depiction of a portrait image was achieved by a novel modulation of the width of micro-apertures in the variable transparency mask. The non-portrait image was encoded as micro-mirrors of an opposing slope and orientation. An optical switch effect between the portrait and a non-portrait image was encoded into the mask by the arrangement of the micro-mirrors as a separate interleaved channel for each image. The lithographic exposure of the pattern into a layer of thick resist has produced an array of micro-mirrors with a depth of 10-30 μm. Various configurations of the micro-mirror arrays have been examined in relation to the type of micro-apertures and their orientation. Optically variable effects achieved in the micro-mirror devices have included a portrait to non-portrait switch, a positive to negative image switch and a non-portrait to non-portrait image switch. The micro-mirror structures have been hot embossed into polypropylene sheet using a Ni shim to create high quality optically variable images.     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Study of RF transistor with submicron T-shaped gate fabricated by nanoimprint lithography

The results devoted to the development of a method for creating an RF transistor, in which a T-shaped gate is formed by nanoimprint lithography, are presented. The characteristics of GaAs p-HEMT transistors have been studied. The developed transistor has a gate “foot” length of the order of 250 nm and a maximum transconductance of more than 350 mS/mm. The maximum frequency of current amplification f _t is 40 GHz at the drain-source voltage V _DS = 1.4 V and the maximum frequency of the power gain f _max is 50 GHz at V _DS = 3 V.     

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Gold nanohole arrays for biochemical sensing fabricated by soft UV nanoimprint lithography

We report on results of fabrication and optical characterisation of sub-250 nm periodic gold nanohole arrays on glass by using UV nanoimprint lithography (UV-NIL) combined with both reactive ion etching (RIE) and Cr/Au lift-off processes. The transmission spectra of the fabricated nanohole gratings were measured for different hole diameters and periods. We also show preliminary results of chemical sensing after surface modification of the gold hole arrays. In agreement with the theoretical prediction, we found that any change in the dielectric index of the surrounding environment of the metallic array produces a transmission peak red shift.     

A common-gate CMOS inverter with n-channel amorphous silicon thin-film transistor formed on a crystalline PMOSFET

A common-gate complementary metal-oxide-semiconductor (CMOS) inverter consisting of an n-channel amorphous silicon (a-Si:H) thin-film transistor on top of 1.2 μm high Al gate of the crystalline silicon p-channel metal-oxide-semiconductor (PMOS) transistor has been achieved successfully. The success of this inverter demonstrates the feasibility of depositing 3500 Å thick amorphous silicon material on a surface with roughness in the order of 1.2 μm. It is found that growing an undoped amorphous silicon layer before the deposition of SiN_x insulator is necessary to avoid the permanent destruction of the underlying PMOS due to the stress imposed by the SiN_x. The vertical integration of crystalline silicon and amorphous silicon devices to form three-dimensional circuits is a promising technique for future applications in high density memory cell and neural network image sensors.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Amorphous silicon thin-film transistor with fluorinated siliconoxide ion stopper

We propose fluorinated silicon oxide (SiOF) as the ion-stopper of bottom-gate amorphous silicon thin film transistors (a-Si:H TFTs). The low dielectric constant SiOF on both the back-channel of the TFT and the crossover regions of gate/data lines can contribute to reducing the RC delay of the gate pulse signal in active-matrix liquid-crystal displays. Besides, the a-Si:H TFT with a SiOF stopper shows an improved performance compared to the widely-employed silicon nitride (SiN_x ) stopper TFT, because the fluorine incorporation reduces the interface state density between a-Si:H and SiOF     

Hydrogenated amorphous silicon carbide double graded-gap p-i-nthin-film light-emitting diodes

Hydrogenated amorphous silicon carbide (a-SiC:H) p-i-n thin-film light-emitting diodes (TFLEDs) with graded p⁺-i and i-n⁺ junctions have been proposed and fabricated successfully on an indium-tin-oxide (ITO)-coated glass. An orange TFLED reveals a brightness of 207 cd/m² at an injection current density of 500 mA/cm². This significant increase of brightness could be ascribed to the combined effect of reduced interface states by using the graded-gap junctions, lower contact resistance due to post-metallization annealing, and higher optical gaps of the doped layers     

Flexible circuit and sensor arrays fabricated by monolithic silicon technology

A novel monolithic batch fabrication method produces arrays of silicon islands containing conventional integrated-circuit components and supported by a flexible polyimide substrate. Islands are interconnected by photolithographically defined gold leads embedded in the polyimide. Because no bonding pads are necessary at island boundaries, lead density between islands is at least twice that available using hybrid techniques. The technology has been used to fabricate thermohaeter arrays for temperature profile measurement during hypertherminal treatment of cancer. An array consists of 20 silicon islands; each island contains one p-n diode, which is used as a thermometer. These linear arrays are 1 mm wide by 0.4 mm thick, with 20-µm-wide by 1-µm-thick gold interconnects on 40-µm centers. The flexible array technology is currently being modified to fabricate two-dimensional arrays of micromechanical sensors for robotic and biomedical uses.     

New developments in amorphous thin-film silicon solar cells

Thin-film silicon solar cells usually contain amorphous silicon layers made by plasma enhanced chemical vapor deposition (PECVD). This CVD method has the advantage that large-area devices can be manufactured at a low processing temperature, thus facilitating low-cost solar cells on glass, metal foil, or polymer foil. In order to obtain higher conversion efficiencies while keeping the manufacturing cost low, a new development is to introduce low bandgap materials in a multijunction device structure. A frequently used low bandgap material is amorphous silicon-germanium. Record initial efficiencies in excess of 15% have been reported for triple-junction solar cells comprising these alloys. In this paper, we present a novel manufacturing method for amorphous silicon based tandem cells suitable for roll-to-roll production     

Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

Single-crystalline silicon thin film on glass (cSOG) has been prepared using an "ion-cutting" based "layer-transfer" technique. Low-temperature processed thin-film transistors, fabricated both on cSOG and metal-induced laterally crystallized polycrystalline silicon, have been characterized and compared. The cSOG-based transistors performed comparatively better, exhibiting a significantly higher electron field-effect mobility (/spl sim/430 cm/sup 2//Vs), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias.     

Vertically integrated amorphous silicon color sensor arrays

Large-area color sensor arrays based on vertically integrated thin-film sensors were realized. The complete color information of each color pixel is detected at the same position of the sensor array without using optical filters. Sensor arrays consist of amorphous silicon thin-film color sensors integrated on top of amorphous silicon readout transistors. The spectral sensitivity of the sensors is controlled by the applied bias voltage. The operating principle of the color sensor arrays and the influence of device design on spectral sensitivity are described. Furthermore, the image quality of the sensor arrays is analyzed by measurements of the line spread function and the modulation transfer function.