On the interior resonance problem when applying a hybrid FEM/MoMapproach to model printed circuit boards

A hybrid finite element method/method of moments (FEM/MoM) technique is used to analyze a printed circuit board power bus structure where the source and observation points are in the near field. The FEM is used to model the lossy region between the planes of the board including the source. The MoM is used to model the region outside the planes and provide a radiation boundary condition to terminate the FEM mesh. Numerical results for a bridged power bus structure are compared with measurements. A nonphysical interior resonance of the electric field integral equation is observed. The problem can be avoided by using a hybrid technique based on a combined field integral equation     

Application of the cavity model to lossy power-return plane structures in printed circuit boards

Power-return plane pairs in printed circuit boards are often modeled as resonant cavities. Cavity models can be used to calculate transfer impedance parameters used to predict levels of power bus noise. Techniques for applying the cavity model to lossy printed circuit board geometries rely on a low-loss assumption in their derivations. Boards that have been designed to damp power bus resonances (e.g., boards with embedded capacitance) generally violate this low-loss assumption. This paper investigates the validity of the cavity model when applied to printed circuit board structures where the board resonances are significantly damped. Cavity modeling results for sample lossy power-return plane structures are validated using a three-dimensional full wave numerical code. A simple method is also established to check the validity of the cavity model for a power-return plane structure with imperfect conductors and lossy dielectric substrates.     

Electromagnetic interference (EMI) reduction from printed circuit boards (PCB) using electromagnetic bandgap structures

As digital circuits become faster and more powerful, direct radiation from the power bus of their printed circuit boards (PCB) becomes a major concern for electromagnetic compatibility engineers. In such multilayer PCBs, the power and ground planes act as radiating microstrip patch antennas, where radiation is caused by fringing electric fields at board edges. In this paper, we introduce an effective method for suppressing PCB radiation from their power bus over an ultrawide range of frequencies by using metallo-dielectric electromagnetic band-gap structures. More specifically, this study focuses on the suppression of radiation from parallel-plate bus structures in high-speed PCBs caused by switching noise, such as simultaneous switching noise, also known as Delta-I noise or ground bounce. This noise consists of unwanted voltage fluctuations on the power bus of a PCB due to resonance of the parallel-plate waveguiding system created by the power bus planes. The techniques introduced here are not limited to the suppression of switching noise and can be extended to any wave propagation between the plates of the power bus. Laboratory PCB prototypes were fabricated and tested revealing appreciable suppression of radiated noise over specific frequency bands of interest, thus, testifying to the effectiveness of this concept.     

Reducing power bus impedance at resonance with lossy components

Power bus structures in printed circuit boards with solid power and ground planes exhibit resonances. When the power bus is resonant, the power bus impedance can increase dramatically. This paper explores the effect of component equivalent series resistance (ESR) on power bus resonances. General guidelines for selecting an optimum ESR are provided and are supported by laboratory measurements and numerical simulations.     

过孔转换信号完整性分析的区域分解有限元法

提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证.     

Modeling of multilayered power distribution planes using transmission matrix method

This paper presents a method for analyzing multilayered rectangular and irregular shaped power distribution planes in the frequency and time domain. The analysis includes the effect of vias on the power distribution network. The planes are modeled using a two dimensional array of distributed RLCG circuit elements. Planes are connected in parallel using vias, which are modeled as self and mutual inductors. For the computation of the power distribution impedances at specific points in the network, a multiinput and multioutput transmission matrix method has been used. This is much faster than Spice and requires smaller memory. Using the transmission matrix method, via effects and the effects of multiple rectangular power/ground plane pairs without and with decoupling capacitors have been analyzed for realistic structures.     

Fast analysis of bounces on power/ground planes using even-odd partition

A novel method for analyzing the bounces on structure of parallel power/ground planes by using the even-odd mode partition is presented in this paper. Based on the distributed RLCG circuit model derived from the two dimensional electromagnetic field equations of the power/ground planar structure, this method can speed up the circuit simulation of the bounces on power/ground planes by using even-odd mode partition. Furthermore, the method can be used to evaluate the effects of the terminated decoupling capacitors and the hole structures on power/ground plane. The numerical examples demonstrate that the method has both high efficiency and good precision.     

The development of a closed-form expression for the input impedance of power-return plane structures

In multilayer printed circuit boards, the noise on the power bus is influenced by the impedance between the power and ground planes. Power-bus noise estimates require an accurate estimate of the power-bus input impedance. This paper develops a closed-form estimate of the input impedance for circular power-return plane structures. When the structure is lossy (e.g., boards employing embedded capacitance or densely populated boards), the energy reflected from the board edge does not significantly affect the input impedance. In general, the expressions developed here for circular structures can be used to estimate the impedance of lossy power-return plane structures of any shape.     

Including dielectric loss in printed circuit models for improvedEMI/EMC predictions

The properties of printed circuit boards (PCBs) pertinent to electromagnetic interference/compatibility (EMI/EMC) are commonly studied using circuit models. This paper describes a method for improving these models by including the effects of frequency-dependent dielectric loss. The approach can be applied to discrete capacitors, microstrips, striplines, power buses, and power planes. The loss terms, which are expressible as frequency-dependent conductances shunting capacitors in the models, can be closely approximated over a wide frequency range as the real part of the driving-point admittance of a resistor-capacitor network. The method is applied to the important case of shunt loss conductance proportional to frequency, but other dielectric classes are as easily treated. An example power bus is analyzed for typical electrical responses, demonstrating the application of this approach, and showing the effect that frequency-dependent dielectric losses can have on the responses     

Modeling the power and ground effects of BGA packages

Ground bounce noise and power supply noise are the major concerns in the electrical design of ball grid array (BGA) packages, therefore accurate models of the package's ground and power structures are needed for circuit simulators. This innovative new software is targeted for the engineer who, at his laptop PC, can rapidly generate accurate power and ground electrical models of an entire BGA package. Using the accepted approximation equations of Grover and Walker [1973 and 1990], the program was designed to be fast and portable contrasting other methods of modeling in which such attributes were sacrificed for greater accuracy. Operation consists of entering the available data, and in just minutes retrieving a parameter listing and two sub-circuit models simultaneously, one circuit for power and one for the ground of the package. The values of inductance and capacitance generated by the program closely match those generated by Grover, Walker, and Caggiano [1995, 1997]. The listing can be used as an evaluation tool for a specific package (e.g., during a design review when critical information is needed quickly) while the circuit models can be used in a simulation program with integrated circuit emphasis (SPICE) circuit simulation of the integrated circuit (IC). These separate models, designed with as few components as possible in order to reduce the complexity of the SPICE topology while still maintaining accuracy, can be either incorporated with signal package models or can be simulated alone     

Simplified modeling of parallel plate resonances on multilayerprinted circuit boards

Multilayer printed circuit boards (PCBs) are currently used in various areas of electronics such as telecommunications. However, high crosstalk between signal vias can cause degradation of performance for these kinds of structures. Resonances of parallel ground or power planes can increase this crosstalk. In this study, a simplified approach to the modeling of these resonances is described. It is assumed that the fields inside the board have characteristically only two-dimensional (2-D) variation. When this hypothesis is valid, it is shown that resonances can be measured on two-layer prototyping boards and simulated using a 2-D finite-difference model. It is additionally noted that a previously suggested method of using coaxial ground vias to suppress coupling between vias is not necessarily effective if there are resonant parallel plates on the board. Agreement between measured and modeled results is good enough for practical design purposes. The main advantages of the method used in this study compared to the more robust three-dimensional (3-D) simulation models are savings in time and costs. Additionally, prototyping is much easier on two than multilayer boards     

Design and simulation of a nanoelectronic single electron 2-4 decoder using a novel simulator

The design and simulation of a single-electron 2-4 decoder using a novel single electron circuit simulation tool named single-electron circuit simulator (SECS), is presented in this paper. In single electron circuits bits of information are represented by the presence or absence of single electrons at conducting or semiconducting islands. SECS utilizes the Monte Carlo method and the change in free-energy of the whole circuit determines the tunnel rates of possible tunnel events, providing thus a real time simulation of any arbitrary single-electron circuit. Furthermore, SECS is using the SPICE interface for schematic capture. SPICE models of single-electron circuit structures have been developed and, therefore, SECS can also be used for the design and simulation of hybrid microelectronic—single-electron circuits.     

A configuration-oriented SPICE model for multiconductortransmission lines with homogeneous dielectrics

Using the SPICE circuit analysis computer program to simulate a lossless multiconductor transmission line is investigated. It is demonstrated that for the case of a homogeneous dielectric, the multiconductor line can be represented by a system of standard two-wire lines which is not based on modal decomposition. This system is readily modeled with SPICE. While restricted to situations where the dielectric constant can be assumed uniform, the present method has the advantage of an intuitive relationship to the conductor configuration, simpler SPICE input data requirements, and an improvement in computer run time over other methods     

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.     

Hybrid analytical modeling method for split power bus in multilayered package

As multiple chips are being integrated into a single package with increased operating frequency, switching noise coupling on power buses has become an important design issue. To reduce the noise coupling, a split power bus structure has been generally used in package substrates having multilayered power and ground planes. Consequently, there is an increasing need for an efficient method to analyze a split power bus in a multilayered package. This paper introduces a hybrid analytical modeling method for characterizing a split power bus in a multilayered package. The proposed method uses a resonant cavity model combined with a segmentation method. Furthermore, a port assignment technique and an associated calculation method for the equivalent circuit model parameter of the split gap are proposed. The proposed port assignment technique and the analytical equation make it possible to analyze a split power bus, especially in a multilayered package. To verify the proposed method, multilayered test packages are fabricated and tested by means of frequency-domain measurements. In addition, an optimal power bus design method was successfully demonstrated for suppressing noise coupling between chips on a single package. Finally, the proposed method and optimal power bus design method was verified using a series of frequency-domain and time-domain measurements.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus     

Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, the authors have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs.     

正负母线均压变换器拓扑电路的设计

本文设计的变换器电路能够在提供辅助电源的同时在硬件上保证母线的平衡。变换器采用单端反激的设计方法,正负母线均衡通过二极管钳位来完成的。本文对拓扑电路的设计方案和变压器等参数进行了详细的描述和计算。实测电路能提供60W的辅助电源能力,正负母线不均衡度为1.8V。此种拓扑电路可以应用在任何母线为±(260-450)V的开关电源上。     

Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.