一种新型双Fin ESD防护单元研究

为满足小尺寸器件的ESD防护需求，基于Fin技术，提出了一种具有寄生SCR的STI双Fin结构。通过采用双Fin布局和深掺杂技术，减小了器件的基区宽度，避免了Fin技术中由弱电导调制导致的SCR无法开启的现象。仿真结果表明，相比于DFSD结构，新结构失效电流I_t2/Wlayout从21.67 mA/μm增加到28.33 mA/μm;触发电压V_t1从14.08 V减小到9.64 V。在ESD来临时，新结构能够实现有效的开启，泄放大电流。     

片上多通道低电容系统级静电防护电路设计

为提高Type-C接口的静电防护性能,提出了基于导流二极管与栅极耦合结构的静电防护架构,用于接口的低压、高压端口.采用齐纳二极管辅助触发的栅极耦合结构(ZCNMOS)泄放静电放电(ESD)大电流,降低触发电压,消除栅接地的NMOS(GGNMOS)中叉指器件不均匀导通的现象;通过大角度离子注入技术,提高器件的ESD防护能...     

保护环版图结构对ESD防护器件耐压能力的影响

基于华润上华0.5 μm双极-CMOS-DMOS (BCD)工艺设计制备了不同保护环分布情况下的叉指型内嵌可控硅整流器的横向扩散金属氧化物半导体(LDMOS-SCR)结构器件,并利用传输线脉冲(TLP)测试比较静电放电(ESD)防护器件的耐压能力.以LDMOS-SCR结构为基础,按照16指、8指、4指和2指设置保护环,形成4种不同类型的版图结构.通过器件的直流仿真分析多指器件的开启情况,利用传输线脉冲测试对比不同保护环版图结构的耐压能力.仿真和测试结果表明,改进后的3类版图结构相对于普遍通用的第一类版图结构,二次击穿电流都有所提升,其中每8指设置一个保护环的版图结构二次击穿电流提升了76.36％,其单位面积的鲁棒性能也最好,为相应工艺设计最高耐压值的ESD防护器件提供了参考结构和方法.     

深亚微米GGNMOS器件ESD鲁棒性的优化与模拟

基于单指条栅接地N型场效应晶体管(GGNMOS)在静电放电(ESD)时的物理级建模方法,仿真分析了版图参数和工艺参数对器件ESD鲁棒性的影响。提出了一种可提高器件ESD保护性能的优化设计,即硅化扩散工艺下带有N阱的多指条GGNMOS结构。对单指条器件模型进行修正,得到的多指条模型能预估不同工艺条件下所需的N阱长度,以满足开启电压V_t1小于热击穿电压V_t2的设计规则。由仿真结果可知,对于一个0.35 μm工艺下的10指条GGNMOS,通过减小栅极长度(L)、提高衬底掺杂浓度(NBC)和漏极掺杂浓度(NE),以及从修正模型中得到合适的N阱长度,均可以增强器件的ESD鲁棒性。     

基于RC触发NMOS器件的ESD电路设计

研究了基于电阻(R)电容(C)触发n型金属氧化物半导体(NMOS)器件的静电放电(ESD)电路参数与结构的设计,讨论了电阻电容触发结构对ESD性能的提升作用,研究了不同RC值对ESD性能的影响以及反相器结构带来的ESD性能差异,并讨论了在特定应用中沟道放电器件的优势。通过一系列ESD测试电路的测试和分析,发现电阻电容触发结构可以明显提高ESD电路的保护能力,其中RC值10 ns设计的栅耦合NMOS(GCNMOS)电路具有最高的单位面积ESD保护能力,达到0.62 mA/μm2。另外对于要求触发电压特别低的应用场合,RC值1μs设计的GCNMOS电路将是最好的选择,ESD能力可以达到0.47 mA/μm2,而触发电压只有3 V。     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。     

GGNMOS叉指宽度与金属布线对ESD防护性能的影响

栅接地NMOS(GGNMOS)器件具有与CMOS工艺兼容的制造优势,广泛用于静电放电(ESD)保护。鉴于目前GGNMOS的叉指宽度、叉指数及金属布线方式等外部因素对ESD鲁棒性的影响研究较少,设计了不同的实验对此开展对比分析。首先,基于0.5μm Bipolar-CMOS-DMOS(BCD)工艺设计并制备了一系列GGNMOS待测器件;其次,通过传输线脉冲测试,分析了叉指宽度与叉指数对GGNMOS器件ESD失效电流(It2)的影响,结果表明,在固定总宽度下适当减小叉指宽度有利于提高It2;最后,比较了平行式与交错式两种金属布线方案对It2的影响,结果表明,平行式金属布线下GGNMOS器件的ESD鲁棒性更好。     

基于有源镇流改善射频功率管的热稳定性

提出一种基于有源电路的基极镇流方案,用以解决射频功率晶体管的电流集中和热稳定性问题.采用传感器检测非均匀结温分布,后级相邻触发电路触发功率器件子单元基极和发射极之间的镇流MOS管,通过分流来缓解电流集中,进而完成器件子单元的过温保护.模拟结果表明,该方案可以有效地实现对功率器件的保护,与传统的无源镇流电阻方法相比,改进后的器件具有更优良的增益特性.单个有源镇流电路仅消耗功率6.5 mW,占用面积为2 530 μm2.     

LDMOS器件软失效分析及优化设计

横向扩散金属氧化物半导体(LDMOS)器件在高压静电放电(ESD)防护过程中易因软失效而降低ESD鲁棒性。基于0.25μm Bipolar-CMOS-DMOS工艺分析了LDMOS器件发生软失效的物理机理,并提出了增强ESD鲁棒性的版图优化方法。首先制备了含N型轻掺杂漏版图的LDMOS器件,传输线脉冲(TLP)测试表明,器件在ESD应力下触发后一旦回滞即发生软失效,漏电流从2.19×10-9 A缓慢增至7.70×10-8 A。接着,对LDMOS器件内部电流密度、空间电荷及电场的分布进行了仿真,通过对比发现电场诱导的体穿通是引起软失效及漏电流增大的主要原因。最后,用深注入的N阱替代N型轻掺杂漏版图制备了LDMOS器件,TLP测试和仿真结果均表明,抑制的体穿通能有效削弱软失效,使其适用于高压功率集成电路的ESD防护。     

一种可切换的双频段CMOS低噪声放大器

基于0.18μm RF CMOS工艺,设计了一种可切换的双频段CMOS低噪声放大器,其输入输出均匹配到50Ω。加入封装、ESD电路和PAD模型,采用Cadence Spectre RF进行仿真。结果显示,在1.8 V工作电压下,1.575 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.9 dB、18.2 dB和5.7 mA;1.2 GHz输入时,LNA的噪声系数、功率增益和偏置电流分别为0.8dB、16.8 dB和5.3 mA。     

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.     

一种f_t为176GHz、大电流多指结构的InGaAs/InP异质结双极晶体管

针对毫米波电路对大电流、高截止频率器件的要求,利用平坦化技术,设计并制作成功了结构紧凑的四指合成InGaAs/InP异质结双极晶体管.实验结果表明发射极的宽度可减小到1μm.Kirk电流可达到110wA,电流增益截止频率达到176GI-Iz.这种器件有望在中等功率的毫米波电路中有所应用.     

Design of multi-finger HBTs with a thermal–electrical model

Multi-finger heterojunction bipolar transistors (HBTs) with uniform spacing exhibit a higher temperature at the center of devices. The temperature distribution on the emitter fingers of the HBT is studied with a three-dimensional thermal–electrical model. Using this model, multi-finger HBTs are designed with non-uniform spacing to improve temperature distribution. Depending on the number of emitter fingers, different design approaches are demonstrated. For a six-finger or 12-finger HBT, the design is more straightforward. For a complex structure such as a 26-finger HBT, an efficient design procedure is necessary. In all of these cases, the calculated results show significant temperature reduction on non-uniform spacing devices.     

RF CMOS modeling: a scalable model of RF-MOSFET with different numbers of fingers

A novel scalable model for multi-finger RF MOSFETs modeling is presented. All the parasitic components,including gate resistance, substrate resistance and wiring capacitance, are directly determined from the layout. This model is further verified using a standard 0.13μm RF CMOS process with nMOSFETs of different numbers of gate fingers, with the per gate width fixed at 2.5 μm and the gate length at 0.13μm. Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.     

Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices

Triggering uniformity and current sharing under TLP stress is investigated in low voltage multi-finger gg-NMOS and NPN ESD protection devices fabricated in smart-power SOI technology. Inhomogeneous current distribution over the fingers and within a single finger is detected by the backside transient interferometric mapping (TIM) technique. 2D TCAD device simulations of the multi-finger devices are used to explain the experimental TIM results. Changes in differential resistance in the pulsed IV characteristics of the NPN ESD protection devices are also explained by TIM experiments.     

Compact distributed multi-finger MOSFET model for circuit-level ESD simulation

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels.     

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5 μm 20 V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4 V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64 mA/μm². The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.