热空穴应力下LDD nMOSFET中GIDL电流退化特性研究*

本文通过GIDL电流参数IDIFF对空穴应力下LDD nMOSFET中的GIDL电流退化进行了深入研究。IDIFF是在相同VDG下漏电压VD=1.4V和栅电压VG=-1.4V两种情形下的GIDL电流之差。空穴陷落在栅漏交叠区的氧化层中导致GIDL电流退化。这些陷落的空穴减小了上述两种对称的测试情形下的横向电场差ΔEX从而使得IDIFF表小。从GIDL电流中提取的IDIFF随着应力时间t的增加而减小。IDIFF的退化量ΔIDIFF,MAX与应力时间成幂指数关系：ΔIDIFF,MAX∝tm, m=0.3. 并用热电子应力实验验证了HHS实验中的相关物理机理。     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2.1nm,栅长为0.135μm的pMOSFET中HALO掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HALO掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HALO掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

不同HALO掺杂剂量的超薄栅pMOSFET的退化

研究了热载流子应力下栅厚为2 .1nm ,栅长为0 .135μm的p MOSFET中HAL O掺杂剂量与器件的退化机制和参数退化的关系.实验发现,器件的退化机制对HAL O掺杂剂量的改变不敏感,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着HAL O掺杂剂量的增加而增加.实验同时发现,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关,而且与阈值电压的退化和应力前阈值电压有关.     

F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系

本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合（G-R）电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合（G-R）电流增大,以及MOSFET饱和漏端电流,亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试,实验观察到饱和漏端电流的线性退化和阈值电压的线性增加,亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。     

90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

A novel experimental technique for the lateral profiling of oxideand interface state charges in hot-hole degraded n-MOSFETs

A new experimental technique, based on gate-to-drain capacitance C _gd^s and charge pumping (CP) current, is proposed for the lateral profiting of oxide and interface state charges in the LDD region of the n-MOSFETs. The device is injected with hot holes, which are subsequently removed by a low-level channel hot-electron stress. The degree of neutralization is monitored by C_gd^s until complete annihilation of trapped holes is realized. This allows the effects of oxide and interface state charges on CP characteristics to be clearly distinguished, and the spatial profiles of the two charges to be separately determined     

Impact of the trapping of anode hot holes on silicon dioxide breakdown

Hot holes are injected from the anode and trapped in thin silicon dioxide using constant voltage stress at large gate voltage. By comparing oxides having trapped holes with oxides in which the holes were detrapped, it is shown that the presence of trapped holes does not affect the breakdown of the oxide. Furthermore, as the temperature during stress is increased, less hole trapping is observed whereas the charge-to-breakdown of the oxide is decreased. The results show that although the trapping of hot holes injected using anode hole injection (AHI) may be partly responsible for defect generation in silicon dioxide, breakdown cannot be limited by the number of holes trapped in the oxide.     

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler–Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.      

Off-state instabilities in thermally nitrided-oxide n-MOSFETs

The significant off-stage gate current of nitrided-oxide n-MOSFETs can be attributed to severe hot-hole injection into the gate oxide during band-to-band (B-B) tunneling due to a nitridation-induced lowering of the barrier height for hole injection. Some of the injected holes are even trapped in the gate oxide above the deep-depletion layer of the drain and thus decrease the gate-induced drain leakage (GIDL) current. A subsequent hot-electron injection into the gate oxide can neutralize these trapped holes and make the reduced GIDL current recover, even increase beyond the original value. The proposed mechanism of the GIDL degradation and recovery behaviors can be confirmed by the observed change in the ratio of the substrate to source currents, as well as by the field-distribution analysis of the gate oxide under stressing     

1.2kV SiC MOSFET器件URS应力退化机理研究

本文首次研究了1.2kV碳化硅(Silicon Carbide,SiC)MOSFET在非钳位重复应力(Unclamped Repetitive Stress,URS)应力下的退化现象,并通过软件仿真和电荷泵测试技术对该现象进行了深入的分析.研究结果表明:URS应力会使得器件积累区由于碰撞电离产生大量的电子空穴对,其中的热空穴将在电场的作用下注入到氧化层中,使氧化层中出现许多空间正电荷,这些空间正电荷的存在使得器件的导通电阻与阈值电压出现下降,关态漏电流出现上升.     

GIDL current degradation in LDD nMOSFET under hot hole stress

The degradation of gate-induced drain leakage（GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter I_DIFF.I_DIFF is the difference of GIDL currents measured under two conditions of drain voltage V_D=1.4 V and gate voltage V_G=-1.4 V while V_DG is fixed.After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region.These trapped holes diminishΔE_X which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make I_DIFF lessening.I_DIFF extracted from GIDL currents decreases with increasing stress time t.The degradation shifts of I_DIFF,MAX(ΔI_DIFF,MAX) follows a power law against t:ΔI_DIFF,MAX∝t^m, m= 0.3.Hot electron stress is performed to validate the related mechanism.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Oxide-trap-induced instability of GIDL of thermally nitrided-oxideN-MOSFET's under stress

Some holes created from band-to-band (B-B) tunneling in the deep-depletion region of the drain can be injected into the gate oxide and reduce the vertical field there. As a result, gate-induced drain leakage (GIDL) current decreases. This kind of hot-hole injection depends on the voltage difference between the drain and gate, due to nitridation-induced lowering of the barrier height for hole injection at the SiO₂-Si interface. The subsequent hot-electron injection can neutralize these trapped holes, and make the GIDL current recover, and even increase beyond its original value. Since the trapped charges also affect the lateral field, the observed change in the ratio of substrate to source currents further confirms the proposed mechanism for the GIDL degradation and recovery behavior     

A hot hole-induced low-level leakage current in thin silicondioxide films

A new kind of stress-induced low-level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the gate edge. Since voltage dependence of this new kind of LLLC is steeper than that of conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in FN stress-induced LLLC. The most promising mechanism is sequential tunneling via trapped holes     

0.275μm nMOST''''s中陷阱辅助隧穿电流对漏端LDD区DCIV谱峰的影响(英文)

应用 direct- currentcurrent voltage(DCIV)和电荷泵 (change pum ping)技术研究了 L DD n MOST’s在热电子应力下产生的界面陷阱 .测试和分析的结果显示 ,一股额外的漏端电流影响了 DCIV谱峰中表征漏区的 D峰 .这股电流主要是陷阱辅助隧穿电流 .