Capacitor loss analysis method for power electronics converters

A capacitor is a major component that contributes to reducing the reliability of high-power density power electronics converters. The lifetime and reliability of capacitors are strongly influenced by temperature. An accurate loss measurement method is necessary to estimate temperature rise. However, practical capacitor loss measurement systems used in power electronics converters have not yet been developed because capacitor loss data provided by the manufacturer is usually measured under sinusoidal excitation, which is different from actual excitations of electronics converters. In this study, a capacitor loss measurement system for power electronics converters is proposed. The proposed measurement system can be used for fast capacitor loss measurement with high accuracy in a real circuit and capacitor loss analysis for each switching period of power electronics converters. To verify the accuracy of the loss measurement, the measured loss value of a filter capacitor used in a pulse width modulated inverter is compared with the calculated value. The experimental results show good agreement with the calculated capacitor loss.     

High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 μA. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 μm CMOS technology to employ the proposed capacitor multiplier.     

X波段MEMS可变电容的设计与制作

对一种适合于X波段通信系统的RF MEMS可变电容进行了结构设计和工艺实现。该电容用高阻硅作为衬底材料,采用凹形和T形梁结构,整个结构由金材料组成;静电驱动,采用驱动信号与微波信号分离的方法。用有限元分析软件Ansys对该电容进行了模拟,随着驱动电压的变化,电容上极板产生位移变化,电容值相应地发生变化;设计了相应的工艺流程,实现了X波段MEMS可变电容的工艺制作和测试,该工艺与集成电路工艺兼容。S参数测试结果表明,在9GHz时Q值可达32.5,电容调节范围为28.8%。     

Area-efficient and self-biased capacitor multiplier for on-chip loop filter

A self-biased capacitor multiplier is proposed to reduce the area of a large integrating capacitor in loop filters. A prototype Sigma-Delta fractional-N frequency synthesiser including the capacitor multiplier is fabricated with a 0.35 mum BiCMOS process. The designed capacitor multiplier makes capacitance of 2.72 nF from an on-chip capacitor of 170 pF with current consumption of 240 muA at 2.8 V. The frequency synthesiser demonstrates the in-band phase noise of -79 dBc/Hz at 5 kHz offset     

A maximum torque control with a controlled capacitor for asingle-phase induction motor

This paper presents a new method to achieve a maximum torque for a single-phase induction motor. An AC adjustable capacitor using an electronic switch in parallel with a capacitor is proposed. The capacitor is short-circuited in a different period by an electronic switch during each cycle to vary the effective value of the AC capacitor. Two new optimization algorithms, which obtain a maximum starting torque by adjusting the effective capacitor, are proposed. No starting capacitor or centrifugal switch is used here. A theoretical analysis, and simulated and experimental results are presented in this paper     

采用金属耦合电容实现级间匹配的射频功率放大器

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available,especially no high density capacitor.To address this problem,a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process.This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal（MIM） capacitor regarding their capacitor density.Detailed simulations are carried out for the leakage,the voltage dependency,the temperature dependency,and the quality factor between an inter-metal shuffled（IMS） capacitor and an MIM capacitor.Finally,an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application.The PA occupies 370 × 200 μm^2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.     

提高钽电容器可靠性的一种新老化方法

通过对钽电容器自愈机理的研究,针对传统老化方法不能彻底剔除电介质有缺陷的钽电容器的缺点,提出一种新的老化方法并对多种钽电容器进行老化实验。新方法可以有效识别并100%剔除电容器不良品,钽电容器生产率提高了50%,钽电容器失效率达到0.1%/(1 000 h),可靠性提高。经验证,这种新老化方法适用于固体电容器、片式钽电容器、聚合物钽电容器和液体钽电容器等多种元件的老化筛选。     

New stack capacitor for dynamic data storage in polysilicon activematrix arrays

A stack capacitor for dynamic circuits employing self-aligned polysilicon thin-film transistors (TFTs) is proposed. Through circuit layout without deviation in processing, a thin-oxide capacitor can be fabricated directly underneath the conventional planar thick-oxide capacitor to form a sandwiched stack capacitor. Due to the addition of the thin-oxide capacitor with high unit capacitance, significant savings in chip area can be achieved. The stack capacitor structure has been successfully demonstrated in polysilicon linear arrays for printer applications. Improved data retention and decreased feedthrough voltage, characteristic of higher storage capacitance, are demonstrated     

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a twostage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 X 200 μm2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.     

微加工射频可变电容的研究与进展

我们给出并比较各种最新颖的可变电容,这些电容包括上极板水平移动的可变电容、梳状水平移动的可变电容、平行板上下移动的可变电容、平行板梳状上下移动的可变电容、改变介质的交叠面积的可变电容、使用水平执行器的可变电容、使用绝缘衬底实现的可变电容和使用MEMS开关调节电容阵列来实现的可变电容,比较了目前的可变电容的各种结构以得出目前工艺条件可以较容易实现的高Q值的可变电容。     

Feed-Through Type Multilayer Capacitor for High Frequency Voltage Noise Suppression

A novel feed-through type multilayer ceramic capacitor (MLCC) is proposed using vertically oriented internal electrodes. The proposed capacitor has a distinctive structure to effectively reduce the parasitic equivalent series inductance (ESL), and thus the noise suppression performance of the capacitor can be greatly improved. Furthermore, it can be made compact with the help of relatively simple terminal structure. Therefore, the capacitor developed here is suitably used as a bypass capacitor in mobile communication systems where miniaturized components with high performance are essentially required. To demonstrate the feasibility and validity of the proposed capacitor, the size 1005 capacitors and evaluation boards have been designed and fabricated. According to the measured results, the proposed capacitor provides the insertion loss of 47.5 dB at 1.0 GHz, and thus the peak to peak voltage noise is reduced from 352 mV to 287 mV by using the proposed capacitor instead of using the regular two terminal MLCC.      

Measurements of leakage currents and the capacitance of the storagecapacitor in a single DRAM cell

Methods of measuring leakage currents and the capacitance of the storage capacitor in a single DRAM cell have been developed for correlation with the electrode shape of the capacitor. In the circuit used for these measurements, the plate electrode of the storage capacitor is connected to the gate of the MOSFET which amplifies the voltage variations of the storage capacitor during the measurements. Here, only a conventional transistor parameter analyzer and a capacitance meter are required for the measurements. For the capacitance measurement, the linear region characteristics of the MOSFET are used to simplify the analysis. For the leakage current measurement, however, the subthreshold region characteristics of the MOSFET are used to enhance the accuracy of the measurement. The results show that the very low leakage currents (down to below 0.1 fA) and the capacitance (37.5 fF) of the storage capacitor can be measured accurately. Further, the leakage current-voltage characteristics of the storage capacitor are discussed by comparing with those of a large area planar capacitor whose structure is the same as the storage capacitor     

NbO电解电容器的结构及制造工艺新进展

较之钽电解电容器,NbO电解电容器电性能更好且价格较低.介绍了NbO电解电容器的结构和制造工艺.从材料及器件制备工艺两方面综述了国内外最近关于NbO电解电容器的研究新进展:通过镁蒸气两步还原法制备流动性较好的NbO粉体;对NbO粉进行掺杂和改性处理;在石墨层和银层中加入导电聚合物层,改善漏电流性能.最后对NbO电解电容...     

薄膜电容器介电强度分析

薄膜电容器是电子仪器中常用的电子元器件,主要用于电视机、显示器、空调、通讯设备、冰箱等设备中。该文介绍了电容器介电强度的概念、电容器介电强度的几个参数即击穿电压、工作电压、试验电压,以及它们之间的关系,介绍了电容器击穿的三种形式即瞬时电压作用下电容器的击穿、电容器的热击穿、在长期电压作用下电容器的击穿——老化击穿。并结合生产实际,总结了提高电容器介电强度的方法。     

用于RDS信号处理的开关电容滤波器的设计

RDS是对FM广播系统应用的重大发展,其接收和解码需要性能较高的开关电容滤波器。通常采用计算z域传递函数,并将其分级用开关电容电路实现的设计方法。这种方法计算复杂,且滤波器的各级结构差异较大。文中提出一种基于重复单元的设计思路,将一个高阶开关电容滤波器拆分为几个结构完全一样的低阶滤波器单元。以二阶连续时间滤波器为基础,用开关电容模拟等效电阻,最终完成一个用于RDS信号处理的八阶开关电容滤波器,简化了设计,但同样具有较好的性能。     

硅基铝T形梁MEMS可变电容的设计与模拟

提出了一种新颖的运用于射频通信系统VCO中的RFMEMS可变电容。该电容使用平行板和T形梁结构,使用硅衬底,整个结构由铝材料组成,结构简单,与集成电路工艺兼容,从而能够实现片上可变电容。通过静电力驱动上极板向下运动,电容值相应地发生改变,当上极板加电压从2.4V变化到4.3V时,电容值从0.25pF变化到0.33pF,变化率为中心电容的27%。使用Coventor软件对该器件进行了模拟,给出的模拟结果包括容量、调节范围、瞬时响应、Pullin电压和运用该可变电容的VCO的电路模拟。     

Two-dimensional numerical model of memory devices with a corrugated capacitor cell structure

A mathematical model of a corrugated capacitor cell (CCC) structure for megabit-class dRAM's is proposed. This model is constructed using a numerical analysis of time-dependent current continuity equations and Poisson's equation. An electrically floating electrode and nonplanar geometries are modeled by zero-current boundary conditions and by Gauss's theorem for Poisson's equation. Transient analyses by a full two-dimensional simulation reveal a complicated device operation mechanism. The storage charge in a floating capacitor is strongly affected by the nearest neighboring capacitor potential, if two storage capacitors are laid out with small pitches. The potential in the floating capacitor significantly shifts when the drive capacitor is charged-up, compared with the reverse case, i.e., a discharge operation for the drive capacitor. A leakage current between two cells was generated due to the electric coupling between them. The current decreases exponentially with respect to the spacing between cells. That is, the electrical coupling strength rapidly decreases with an increase in the spacing. The present model can be highly applicable for designing dRAM devices with complicated and highly integrated structures. Design criteria are clarified.     

CMOS low dropout regulator with dynamic zero compensation

The output capacitor and its equivalent series resistance (ESR) often limit the stability of a conventional low dropout regulator (LDR). A CMOS LDR with dynamic zero compensation is presented to tolerate the wide range of the output capacitor and the ESR. The stability constraints for the output capacitor with the ESR are derived. The measured LDR is stable for the output capacitor 2nF-47uF with ESR of 0.1-50Omega. The maximum quiescent current of this LDR with a bandgap reference is 43.2uA and its maximum output current is 150 mA for the output voltage of 1.8V.     

一种连续可调接地电容倍比器的实现

提出了一种用电流传送器 (CC +/-)构成的接地电容倍比器。该倍比器的电容量可经接地电阻连续调节 ,线性可调范围大 ,利用此接地电容 ,另添加一个电阻 ,可构成一阶低通滤波器 ,改变接地电阻的大小 ,即改变了滤波器的 -3 d B截止频率 ,计算机仿真结果与理论分析相吻合     

TFT阵列基板的电容充电电路的设计

液晶显示器尺寸越来越大,液晶栅极启动信号持续时间变短,液晶电容和存储电容的充电时间也随之减少,导致对液晶电容和存储电容充电不充分,造成横向微弱亮线的产生,使得画面品质下降。本文设计出TFT阵列基板电容充电电路,在当前行像素显示时,对下一行像素预充电,解决了液晶电容和存储电容充电不充分的问题。