Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects

The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.     

Simulating the current mirror with a self-heating BJT model

A Gummel-Poon (GP) BJT (bipolar junction transistor) model that includes self-heating is presented, and a current-mirror circuit is used to show its significance. Self-heating thermal effects are modeled by a simple electrical analog circuit, which also provides BJT junction temperature as part of the CAD solution. Both discrete-BJT and IC mirror circuits are tested. The self-heating model correctly simulates the temperature stability of the IC mirror circuit where the BJTs are in close thermal proximity. For the discrete-BJT circuit, a standard GP model produces errors up to 84% versus 6.1% for the self-heating model     

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.     

Characterization of layout dependent thermal coupling in SOI CMOScurrent mirrors

A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 μm SOI CMOS technology, with devices separated by as much as 20 μm. Measurements were verified by electro-thermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies     

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

Impact of self-heating and thermal coupling on analog circuits inSOI CMOS

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-μm SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage     

SOI thermal impedance extraction methodology and its significancefor circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R_th) and thermal capacitance (C_th) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Direct extraction of MOSFET dynamic thermal characteristics from standard transistor structures using small signal measurements

A method is presented for directly obtaining the temperature rise in MOSFETs due to channel current self-heating. The technique is based on small signal measurements, and also provides thermal time-constant data. No special layout structures are needed, making it suitable for bulk and SOI technologies. Experimental results are compared with data obtained using thermal noise measurements with a special SOI MOSFET, and the two figures show good agreement.<>     

Electro-thermal simulation of current sharing in silicon and silicon carbide power modules under short circuit condition of types I and II

Current sharing during short circuit events of types I and II has been investigated by electro-thermal compact simulation of semiconductor devices paralleled in a 650 V power module. The response of silicon IGBTs has been compared to that of silicon carbide MOSFETs. The study of current unbalance due to symmetrical and asymmetrical interconnect topologies has been followed by isothermal and full electro-thermal simulation of the power modules. It has been shown that replacing in the simulation the active devices within the module by resistors leads to misleading results, because the current unbalance under short circuit conditions is mainly due to the difference in the gate-source/gate-emitter voltage among the individual paralleled devices. Finally, it has been demonstrated that in the investigated power modules, self-heating contributes to the mitigation of current unbalance.     

Electro-thermal and logi-thermal simulation of VLSI designs

Due to severe thermal problems of today's VLSI integrated circuits the need for reliable and quick thermal, electro-thermal and logi-thermal simulation tools is increasing, In this paper, we discuss the latest advances in the SISSI package (simulator for integrated structures by simultaneous iteration) which is a tool developed originally for analog VLSI design. The improvements include electro-thermal ac and transient simulation and the consideration of the thermal voltage of Si-Al contacts. Furthermore, we introduce a new module of SISSI, LOGITHERM, which is aimed at the self-consistent logic and thermal simulation of large digital VLSI designs. The features of our simulator package are highlighted by simulation examples that are compared in most cases with measurement results     

Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.     

B-Spline Based, Large-Signal DC and Microwave-Model for SOI MOSFETs

We present a large/small-signal, non-quasi-static, charge conserving, SOI MOSFET modeling technique suitable for DC and high frequency circuit design. The device model is extracted from small signal microwave iso-thermal Y-parameter data and DC I–V characteristics. Low frequency dispersions associated with self-heating and floating body effects are verified to not limit the performance of this technique since it relies on both DC and transient I–V characteristics. The technique is applied to the modeling of a short-channel, partially depleted, SOI nMOSFET simulated on PISCES. The model generated is incorporated into a circuit simulator, which is used to perform large-signal transient and harmonic balance simulations. The transient I–V and gate charge extracted from the iso-thermal small-signal microwave Y-parameters, are in excellent agreement with the iso-thermal transient I–V and gate charge obtained from PISCES, respectively. The model topology is extended with a parasitic bipolar sub-circuit which automatically calculates the DC operating point for self-biasing circuits. Transient and non-linear power characterization results predicted with this model agree well with those obtained from PISCES for a wide range of input power drives. A complete electro-thermal model is proposed and verified to be able to predict temperature and transient I–V response.     

Deep submicron PDSOI thermal resistance extraction

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.     

Fully coupled electrothermal mixed-mode device simulation of SiGeHBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the μA709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation     

Heating effects of clock drivers in bulk, SOI, and 3-D CMOS

Steady-state and transient thermal behavior of the highest power density element in systems and chips-the clock driver-in bulk, silicon-on-insulator (SOI), and three-dimensional (3-D) CMOS is examined. Despite significant metal wiring, a majority of the heat conducts through the buried oxide (BOX) in SOI and the buried interconnect layer in 3-D CMOS. 3-D CMOS has the potential to improve substantially over SOI CMOS in thermal behavior by increasing the wiring density directly beneath the clock driver. Temperature mismatch (important for analog applications) between device planes in 3-D CMOS occurs within a characteristic length, which is as large as 13 /spl mu/m for clock drivers. These results suggest advantages and architectural options for the design of high-power devices in 3-D integration.     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

Simulation of LED based luminaires by using multi-domain compact models of LEDs and compact thermal models of their thermal environment

Fast and accurate prediction of hot lumens of LEDs installed in luminaires is an important step in the design of robust and reliable products. A possible approach to this is to create a multi-domain circuit model of a complete LED chip + package + luminaire system that can be simulated by any Spice-like circuit simulator with electro-thermal capabilities. Many LED chip and LED package models and modeling techniques have been published recently, but compact thermal modeling of luminaires as multi heat-source system was not yet dealt with in the literature. This paper aims to fill this gap be describing a systematic approach for system (luminaire) level analysis aimed at solving the combined thermal, electrical and light output simulation problem consistently by describing a method for creating a compact thermal model of LED luminaries with an approach borrowed from the layout based electro-thermal simulation of analog ICs. The applicability of the described method is demonstrated with a real life example, including the validation of the results with thermal measurements.     

Physical modeling of temperature dependences of SOI CMOS devicesand circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature     

Design methodology for over-temperature and over-current protection of an LDO voltage regulator by using electro-thermal simulations

This paper presents a methodology for designing over-temperature and over-current protection (OTP and OCP) circuits for low drop-out voltage regulators (LDOs). The OTP monitors the die temperature developed within the LDO and disables its output stage when the temperature reaches a certain, user-defined, level (the OTP activation point). If the LDO output current reaches a set threshold (the OCP activation point), the OCP takes control of it, keeping the current value to an acceptable level. The proposed methodology involves running iteratively electrical, thermal and electro-thermal simulations. It addresses three major issues: first, it allows the designer to identify the suitable layout placement of the OTP and OCP sensors, based on the temperature distribution within the LDO power-stage. Second, the OTP and OCP activation points can be set accurately by taking into account coupled electro-thermal phenomena and the unavoidable differences between the temperature and current sensed by the protection circuits and those developed within the worst-case LDO section. Finally, the LDO design can be fine-tuned considering complex scenarios of real-life operation and test requirements. An LDO was designed using this methodology and the paper provides a direct comparison between the expected (simulated) results and measurements performed on the silicon implementation.