Super-regenerative receiver at 433 MHz

This paper presents a receiver for operation in the 433 MHz ISM band. The selected architecture explores the super-regeneration phenomena to achieve a high sensitivity for applying in wireless implantable microsystems. This radio-frequency (RF) chip can be supplied with a voltage of only 3 V for demodulating signals with powers in the range (−100, −40) dB. The codulation (modulation and coding) scheme of the binary data is a variation of the Manchester code combined with on/off keying (OOK) modulation. The AMIS 0.7 μm CMOS process was selected for targeting the requirement to fabricate a low-cost receiver, whose prototype was integrated in a die with an area of 5×5 mm². Also, this receiver is fully compatible with commercial transmitters for the same frequency.     

Photomodulated transmittance of GaBiAs layers grown on (0 0 1) and (3 1 1)B GaAs substrates

In this work, photomodulated transmittance (PT) has been applied to investigate the energy gap of GaBiAs layers grown on (0 0 1) and (3 1 1)B GaAs substrates. In PT spectra, a clear resonance has been observed below the GaAs edge. This resonance has been attributed to the energy gap-related absorption in GaBiAs. The energy and broadening of PT resonances have been determined using a standard approach in electromodulation spectroscopy. It has been found that the crystallographic orientation of GaAs substrate influences on the incorporation of Bi atoms into GaAs and quality of GaBiAs layers. The Bi-related energy gap reduction has been determined to be ∼90 meV per percent of Bi. In addition to PT spectra, common transmittance spectra have been measured and the energy gap of GaBiAs has been determined from the square of the absorption coefficient α² around the band-gap edge. It has been found that the tail of density of states is significant for GaBiAs and influences the accuracy of energy gap determination from the α² plot. In the case of PT spectra, the energy gap is determined unambiguously since this technique is directly sensitive to singularities in the density of states.     

The effects of 12 MeV electron irradiation on the electrical characteristics of the Au/Aniline blue/p-Si/Al device

An Au/Aniline blue (AB)/p-Si/Al structure has been fabricated and then the effect of electron irradiation (12 MeV electron energy and 5 × 10¹² e⁻ cm⁻² fluence) on the contact parameters of the device has been analysed by using the current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G/w-V) measurements, at room temperature. Since the organic layer creates a physical barrier between the metal and the semiconductor, it has been seen that the AB layer causes an increase in the effective barrier height of the device. Cheung functions, Norde model and conductance method have been used in order to determine the diode parameters. The values of the ideality factor, barrier height and series resistance increased after the electron irradiation. This has been attributed to a decrease in the net ionized dopant concentration that occurred as a result of electron irradiation.     

A tunable highly linear CMOS transconductor with 80 dB of SFDR

This paper presents a new tunable CMOS differential transconductor with an SFDR ranging from 80 to 94 dB. It is based on a core of two voltage buffers with local feedback loops to achieve low-output impedance. The two buffers drive an integrated polysilicon resistor, which is the actual transconductance element. The current generated at the resistor is delivered directly to the output using source coupled pairs. This avoids distortion generated by conventional architectures using current copying cells. The voltage buffers are based on the compact flipped voltage follower (FVF) cell. The proposed transconductor relies on the gain of local feedback loops instead of harmonic cancellation. This leads to a simpler design and less mismatch sensitivity. The proposed transconductor bandwidth is closer to that of the typical open-loop design than to one with global feedback, since the local feedback loop is much faster than a global one. It can be tuned down 20% of its maximum g_m which is enough to compensate for process variations. The proposed circuit was fabricated in a 0.5 μm CMOS technology and powered by a 5 V single supply. It was measured with 2 Vpp input signals up to 10 MHz. The maximum g_m value is 660 μA/V. The transconductor consumes 30 mW and occupies roughly a die area of 0.17 mm². Experimental results are presented to validate the proposed circuit.     

New design of low power, 100 Mb-s IR-UWB pulse generator in 0.18 µm CMOS technology

A new method of impulse radio ultra-wideband (IR-UWB) pulse generation, with advantage of providing a “notch” like representation of pulse in the spectrum domain for particular control parameters values, is investigated in this paper. Low power pulse generator is composed of a glitch generator, a switched oscillator, a two-stage buffer and a pulse shaping filter. The proposed architecture, designed in UMC 0.18 µm CMOS technology, can operate in a single band from 3.3 GHz to 9.3 GHz or in a double, lower and higher UWB band (from 3 GHz to 9.15 GHz), suppressing frequencies in the WLAN band. Both spectrums fully comply with the corresponding FCC spectral mask, while the pulse generator regime and the spectrum range are determined by control signal values. Post-layout simulation results showed a pulse width of 0.5 ns, and a peak-to-peak amplitude of 211 mV for one band spectrum. The average power consumption is 0.89 mW corresponding to the energy consumption of 8.9 pJ/pulse for 100 MHz pulse repetition rate (PRF). The pulse duration is 1 ns and peak-to-peak amplitude is 202 mV in the case of the WLAN frequency band suppression. The total chip area is 0.31 mm². The pulse generator has been evaluated for the best performance supporting the on-off keying (OOK) modulation.     

A 7-bit 500 kS/s 1 V micro-power SAR A/D converter for pixel systems

The design and measurement results of a micro-power successive approximation charge redistribution ADC implemented in CMOS 180 nm technology are presented. The project has been optimized for very low area occupancy in order to utilize it in multichannel neural signal recording pixel systems for future application. The design has been fabricated, experimentally characterized and it exhibits good performance, especially from the silicon area occupation point of view. The presented converter achieves 500 kS/s sampling rate with ENOB of 6.54 at 4.45 μW and occupies only 90 μm×95 μm of silicon area.     

Studies of Ti- and Ni-germanide Schottky contacts on n-Ge(1 0 0) substrates

In this study, we investigated fabrication and characteristics of germanides Schottky contacts on germanium. Ti- and Ni-germanides were fabricated on n-Ge(1 0 0) substrates by sputtering metal Ti or Ni on Ge followed by a furnace annealing. The influence of annealing temperature on the electrical properties of Ti- and Ni-germanide on n-Ge(1 0 0) substrates was investigated. The low temperature ∼300 °C annealing helped to obtain the optimized Schottky contact characteristics in both Ti-germanide/Ge and Ni-germanide/Ge substrates contacts. The well-behaved Ti-germanides/n-Ge Schottky contact with 0.34 eV barrier height was obtained by using a 300 °C annealing process.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO₂ gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

AP-MOVPE of InGaAs on GaAs (0 0 1): Analysis of in situ reflectivity response

We have investigated in situ monitoring of growth rate and refractive index by laser reflectometry during InGaAs on GaAs (0 0 1) substrate growth in atmospheric pressure metalorganic vapour-phase epitaxy (AP-MOVPE). The indium solid composition (x_In^s) was varied by changing the substrate temperature or the indium vapour composition (x_In^v). The refractive index of InGaAs alloys as a function of temperature and composition was quantified and compared which that of GaAs for 632.8 nm wavelength by simulation of experimental reflectivity responses. Composition analyses were carried out by high-resolution X-ray diffraction (HRXRD) and optical absorption (OA). The layers thicknesses were estimated by scanning electron microscopy (SEM) observations. The temperature dependence of InGaAs growth rate has been investigated in the temperature range 420-680 °C using trimethylgallium (TMGa), trimethylindium (TMIn) and arsine (AsH₃) sources. It shows Arrhenius-type behaviour with an apparent activation energy E_a of 0.62 eV (14.26 kcal/mol). This value is close to that determinate in the AP-MOVPE of GaAs.     

Performance enhancement in Ge pMOSFETs with <1 0 0> orientation fabricated with a Si-compatible process flow

The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm²/V s for <1 1 0> devices to 210 cm²/V s for the <1 0 0> oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H₂ ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of D_it, improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.     

Design and implementation of a 0.8 V input, 84% duty cycle, variable frequency step-up converter

A 0.8 V input, 84% duty cycle, variable frequency CMOS DC-DC step-up converter with integrated power switches has been presented in this paper. The converter has the properties of both the current mode and hysteric control mode operations. The inductor charging time of the topology is designed to be inversely proportional to the input voltage and as a result the inductor current disturbance dies out immediately. Hence, no external components and extra I/O pins are required for the compensation of the current loop. The step-up converter has been fabricated with a standard pseudo BiCMOS process. Special MOS device of threshold voltage 0.5 V and start-up circuitries enable the converter to start from a voltage as low as 0.8 V. The real time data show that the converter can boost 0.8 V to as high as 5 V, which makes it suitable for low voltage applications. The efficiency of the chip has been found over 75 % for the entire load range from 10 to 100 mA.     

Crystalline orientation dependence of electrical properties of Mn Germanide/Ge(1 1 1) and (0 0 1) Schottky contacts

We have investigated the crystalline orientation dependence of the electrical properties of Mn germanide/Ge(1 1 1) and (0 0 1) Schottky contacts. We prepared epitaxial and polycrystalline Mn₅Ge₃ layers on Ge(1 1 1) and (0 0 1) substrates, respectively. The Schottky barrier height (SBH) estimated from the current density-voltage characteristics for epitaxial Mn₅Ge₃/Ge(1 1 1) is as low as 0.30 eV, while the SBH of polycrystalline Mn₅Ge₃/Ge(0 0 1) is higher than 0.56 eV. On the other hand, the SBH estimated from capacitance-voltage characteristics are higher than 0.6 eV for both samples. The difference of these SBHs can be explained by the local carrier conduction through the small area with the low SBH regions in the epitaxial Mn₅Ge₃/Ge(1 1 1) contact. This result suggests the possibility that the lowering SBH takes place due to Fermi level depinning in epitaxial germanide/Ge(1 1 1) contacts.     

A 6.9 mA 5 bits 90 nm 1 GS/s ADC without calibration for UWB application

Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1 Gs/s ADC without calibration, realized in a 90 nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9 mA from a 1.2 V supply.     

Epitaxial growth of Fe/MgO/Ge(0 0 1) heterostructures

We report on the growth of epitaxial Fe/MgO heterostructures on Ge(0 0 1) by Molecular Beam Epitaxy. The better crystal quality and interfacial chemical sharpness at the oxide-semiconductor interface have been obtained by growing MgO at room temperature, followed by a post-annealing at 773 K, on top of a p(2 × 1)-Ge(0 0 1) clean surface. The growth of Fe at room temperature followed by annealing at 473 K gives the best epitaxial structure with optimized crystallinity of each layer compatible with limited chemical interdiffusion. Tunneling devices based on the epitaxial Fe/MgO/Ge heterostructure have been micro-fabricated and tested in order to probe the electrical properties of the MgO barrier. The current-voltage characteristics clearly show that tunneling is the dominant phenomenon, thus indicating that this system is very promising for practical applications in electronics and spintronics.     

Growth mechanism of iron nanoparticles on (0 0 0 1) sapphire wafers

Laser ablation of a high purity (99.7%) iron target was used to accomplish the depositions of iron nanoparticles on the (0 0 0 1) face of single crystal sapphire wafers. The nanoparticles were characterized in situ by means of X-ray photoelectron spectroscopy (XPS). The growth mechanism was determined by applying the QUASES-Tougaard methodology to the extended part of the background intensity of the Fe KMM peak in XPS spectra. The heights of nanoparticles obtained are between 3.5 and 6.5 nm. In the first 150 laser pulses, the height of the nanoparticles remained constant while the coverage was increased.     

Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.