Local crystal structural modifications in pulsed laser deposited high-k dielectric thin films on silicon and germanium

The thin film growth conditions are correlated with the local structures formed in Hf_xZr_1−xO₂ (x=0.0–1.0) high-k dielectric thin films on Si and Ge substrates during deposition. Pulsed laser deposition (PLD) technique has been used in the synthesis of the thin films with systematic variations of substrate temperature, Zr content of the targets and substrate selection. The local structural information acquired from extended X-ray absorption spectroscopy (EXAFS) is correlated with the thin film growth conditions. The response of the local structure around Hf and Zr atoms to growth parameters was investigated by EXAFS experiments performed at the National Synchrotron Light Source of Brookhaven National Laboratory. The competing crystal phases of oxides of Hf were identified and the intricate relation between the stabilized phase and the parameters as: the substrate temperature; Hf to Zr ratio; have been revealed. Specifically, HfO₂ thin films on Si(1 0 0) exhibit a tetragonal to monoclinic phase transformation upon increase in the substrate temperature during deposition whereas, HfO₂ PLD films on Ge(1 0 0) substrates remain in tetragonal symmetry regardless of the substrate temperature.     

Behaviour of injected electrons in high-k dielectric layers

The programming operation in memory device consists of an injection of electrons into the gate dielectric (GD). In many cases, oxide–nitride–oxide (ONO) is used as a GD. A stability of the spatial profile of injected electrons (IE) determines the quality of the memory device. Computer simulations showed that injection of electrons into GD leads to the formation of small charge droplets out of the initial spatial profile of IE. Such a droplet is named as parasitic peak (PP). The simulation of IE redistribution in GD shows that the Coulomb scattering of newly injected carriers on PPs plays an important role in the evolution of the device parameters in conditions of long-term exploitation. The computer model of ONO with high-k layers (HKL) is developed to study the retention parameters of the device in dependence on the type of HKL and on the thickness of GD. The influence of scaling down of the dielectric film with HKL on IE redistribution in GD is investigated. Simulations showed that the possibility of scaling down the thickness of ONO stack with HKL depends not only on the tunnelling effects but also on the multiple scattering processes in ONO with HKL.     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Atomic oxygen-assisted molecular beam deposition of Gd2O3 films for ultra-scaled Ge-based electronic devices

The atomic oxygen-assisted molecular beam deposition of Gd₂O₃ films on Ge(0 0 1) substrates has been performed at various growth temperatures. The compositional aspects, the interface details and the surface structure have been investigated by in situ X-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectroscopy and in situ atomic force microscopy, and ex situ. The interface layer of GeO₂ has been subsequently fabricated by means of atomic oxygen exposure in order to passivate the high-k/Ge interface. The electrical characterization on the final Gd₂O₃/GeO₂/Ge structure has been reported. The electrical characterization on the Al gate/Gd₂O₃/GeO₂/Ge structure exhibits a MOS behavior, indicating the beneficial effect of GeO₂ passivation.     

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO₂/HfAlO/SiO₂ triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.