A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

GaN-based optoelectronic devices on sapphire and Si substrates

A recessed gate AlGaN/GaN high-electron mobility transistor (HEMT) on sapphire (0 0 0 1), a GaN metal-semiconductor field-effect transistor (MESFET) and an InGaN multiple-quantum well green light-emitting diode (LED) on Si (1 1 1) substrates have been grown by metalorganic chemical vapor deposition. The AlGaN/GaN intermediate layers have been used for the growth of GaN MESFET and LED on Si substrates. A two-dimensional electron gas mobility as high as 9260 cm²/V s with a sheet carrier density of 4.8×10¹² cm⁻² was measured at 4.6 K for the AlGaN/GaN heterostructure on the sapphire substrate. The recessed gate device on sapphire showed a maximum extrinsic transconductance of 146 mS/mm and a drain–source current of 900 mA/mm for the AlGaN/GaN HEMT with a gate length of 2.1 μm at 25°C. The GaN MESFET on Si showed a maximum extrinsic transconductance of 25 mS/mm and a drain–source current of 169 mA/mm with a complete pinch-off for the 2.5-μm-gate length. The LED on Si exhibited an operating voltage of 18 V, a series resistance of 300 Ω, an optical output power of 10 μW and a peak emission wavelength of 505 nm with a full-width at half-maximum of 33 nm at 20 mA drive current.     

Study of dc conduction mechanisms in dysprosium–manganese oxide insulator thin films grown on Si substrates

Samples of amorphous and crystalline (Dy–Mn) oxide thin films have been prepared on Si(p) substrates. The crystal structure of the oxide film annealed under different conditions was investigated by the X-ray diffraction method (XRD). The percentage weight composition of the compound-oxide films was determined by the X-ray fluorescence (XRF) spectroscopy method. It was observed that Dy oxide and Mn oxide prevent each other to crystallize alone or making a solid solution even at 600 °C, but a compound of DyMnO₃ was formed through the solid-state reaction at T > 800 °C. Samples in form of Al/oxide/Si MOS structures were characterised by measuring their capacitance as a function of gate voltage C(V_g) in order to determine the fixed and interface charge densities as well as the oxide voltage in terms of gate voltage. The total surface charge density was in the device-grade of 10¹⁰–10¹¹ cm⁻². The dc measurements at room temperature show that the main mechanism controlling the current flow is the Richardson–Schottky (RS) mechanism. The parameters of the RS model like the field lowering coefficients and the dynamic relative permittivity were determined. The leakage current density of the samples was studied as a function of temperature in a range of (293–380 K). It was observed that the temperature dependence of crystalline (Dy–Mn) oxide films has a property that higher temperature reduces the current, which may be important in the application in circuits that operate under extreme conditions. Thermal activation energies of electrical conduction were determined.     

Characterization of SiC MESFETs with narrow channel layer

SiC MESFETs with a narrow channel layer are proposed to alleviate the short-channel effects, in particular the drain-induced barrier lowering (DIBL) effect that results in threshold voltage that is dependent on the gate length and the drain voltage applied. Such narrow channel layer 4H-SiC MESFETs were fabricated and characterized. The thickness and doping concentration of the channel layer are 0.08 μm and 8.0 × 10¹⁷ cm⁻³, respectively. The measurement results showed that the threshold voltage of the MESFETs is about −1.1 V and is independent of the gate length from 1 to 3 μm, and the drain voltage applied up to 40 V. Good saturation behavior with fairly low output conductance was also achieved, which is desirable for small signal applications. The results obtained for the narrow channel layer MESFETs are also compared with those measured for conventional devices with thicker channel layer of 0.20 μm and doping concentration of 2.5 × 10¹⁷ cm⁻³.     

The separation of generation lifetimes of Si and SiGe using capacitance-transient measurements on MOS capacitors formed by plasma anodisation of Si:Si0.9Ge0.1:Si substrates

A simple technique leading to the measurement of minority carrier lifetimes of UHV compatible LPCVD Si and SiGe by C–t depth profiling of Metal:Oxide:Si:SiGe:Si structures is reported. A high quality gate oxide is realised by low temperature (<100°C) plasma anodisation thereby reducing any oxidation effects on the underlying epitaxial layer quality. Capacitance response times were observed for an impurity concentration of 2.5×10¹⁷ cm⁻³, giving rise to generation lifetimes of the Si and Si_0.9Ge_0.1 of >0.55 and 2.6 μs respectively, reflective of very high quality epitaxial semiconductor material.     

Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

In this work, the effects of voltage and temperature on the TDDB characteristics of 2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (t_BD) are recorded from p⁺-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The t_BD cumulative distributions exhibit a single Weibull slope β of 1.9 for different applied voltages. The charge-to-breakdown (Q_BD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm² on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of 14.83 V⁻¹. It is projected that the maximum safe operating voltage is 1.9 V for 2.07 nm O/N gate dielectric.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.     

Ultrathin CdSe nanowire field-effect transistors

We report the fabrication, and electrical and optical characterization, of solution-liquid-solid (SLS) grown CdSe nanowire field-effect transistors. Ultrathin nanowires (7–12 nm diameters) with lengths between 1 μm and 10 μm were grown by the SLS technique. Al-CdSe-Al junctions are then defined over oxidized Si substrate using photolithography. The nanowires, which were very resistive in the dark, showed pronounced photoconductivity even with a visible light source with resistance decreasing by a factor of 2–100 for different devices. Field-effect devices fabricated by a global backgating technique showed threshold voltages between −7.5 V and −2.5 V and on-to-off channel current ratios between 10³ and 10⁶ at room temperature. Channel current modulation with gate voltage is observed with the current turning off for negative gate bias, suggesting unintentional n-type doping. Further, optical illumination resulted in the loss of gate control over the channel current of the field-effect transistor.     

Ballistic electron emission microscopy studies of the temperature dependence of Schottky barrier height distribution in CoSi2/n-Si(1 0 0) diodes formed by solid phase reaction

Ballistic electron emission microscopy (BEEM) and ballistic electron emission spectroscopy have been performed on polycrystalline and epitaxial CoSi₂/n-Si(1 0 0) contacts at temperatures ranging from −144°C to −20°C. The ultra-thin CoSi₂ films (10 nm) were fabricated by solid state reaction of a single layer of Co (3 nm) or a multilayer of Ti (1 nm)/Co (3 nm)/amorphous-Si(1 nm)/Ti (1 nm) with a Si substrate, respectively. The spatial distribution of barrier height over the contact area obeys a Gaussian function at each temperature. The mean barrier height increases almost linearly with decreasing temperature with a coefficient of −0.23±0.02 meV/K for polycrystalline CoSi₂/Si diodes and −0.13±0.03 meV/K for epitaxial diodes. This is approximately equal to one or one-half of the temperature coefficient of the indirect energy gap in Si, respectively. It suggests that the Fermi level is pinned to different band positions of Si. The width of the Gaussian distribution is about 30–40 meV, without clear dependence on the temperature. The results obtained from conventional current–voltage and capacitance–voltage (I–V/C–V) measurements are compared to BEEM results.     

Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10⁶ h. In the ramped-voltage tests, 10×10 μm² capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm² capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10⁹ h, while only 0.07% of the population has MTTF less than 1×10⁶ h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.     

Flexible complementary inverter with low-temperature processable polymeric gate dielectric on a plastic substrate

We report low-temperature processability of poly(4-vinylphenol) based gate dielectric by investigating the effect of composition and processing temperature on the thermal, mechanical and electrical characteristics of the gate dielectric. We found that the processing temperature of the gate dielectric could be reduced up to 70 °C by optimizing the composition of the gate dielectric solution. Based on this finding, we have fabricated a flexible organic complementary inverter by integrating n- and p-type organic thin-film transistors (OTFTs) with the low-temperature processable gate dielectric on a plastic substrate. Pentacene and F16CuPc were used as p-type and n-type semiconductor, respectively. The inverter shows that the swing range of V_out is same as V_DD, which ensures “zero” static power consumption in digital circuits. The logic threshold of the inverter with G5 gate dielectric cured at 70 °C is 21.0 V and the maximum voltage gain (∂V_out/∂V_in) of 8.1 is obtained at V_in = 21.0 V. In addition, we have discussed in more detail the characteristics of the OTFTs and the complementary inverter with respect to the process condition of the gate dielectric.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Optical dispersion analysis within the IR range of thermally grown and TEOS deposited SiO2 films

SiO₂ thin films, with thickness ranging between approximately 13 and 95 nm, have been thermally grown at 950°C in dry oxygen and chemically vapor deposited at low pressures (0.3 Torr) by decomposition of tetraethylorthosilicate (TEOS) at 710°C, on Si (100) substrates. Dispersion analysis was performed on Fourier transform infrared (FTIR) transmission spectra of these films within the range 900–1400 cm⁻¹. It was found that the spectra were best described within this range, by four Lorentz oscillators located near 1060, 1089, 1165 and 1220 cm⁻¹ almost independent of film thickness. The polarization of the oscillators (proportional to their strength) was found to increase slightly, and their widths to decrease, with film thickness. From the study of the FTIR spectra obtained at room temperature, it was suggested that at this temperature, a considerable number of Si–O–Si angles in these SiO₂ films are distributed in a way expected at higher temperatures and that the distribution of the Si–O–Si angles depends on the thermal history of the film and the method of growth.     

Field- and current-driven degradation of GaN-based power HEMTs with p-GaN gate: Dependence on Mg-doping level

Within this paper we investigate the degradation of GaN-HEMTs with p-GaN gate submitted to stress at forward gate bias. We studied the effect of both constant-voltage stress and short-pulse stress (induced by TLP, Transmission Line Pulser); devices having three different Mg-doping levels (ranging from 2.1 · 10¹⁹/cm³ to 2.9 · 10¹⁹/cm³) were used for the study.We demonstrated the existence of two different degradation mechanisms, depending on the stress conditions: (i) when submitted to TLP stress (100 ns pulses with increasing amplitude), the failure occurs through a field-driven process, i.e. the breakdown of the metal/p-GaN Schottky junction, which is reversely biased when the gate is at positive voltage. Failure voltage decreases with increasing Mg doping, since higher acceptor levels result in a higher electric field. (ii) Conversely, during constant-voltage stress, the long-term stability is undermined by a current-driven process, namely the accumulation of positive charges at the p-GaN/AlGaN interface, which promotes an increase of the leakage current, first gradual and then catastrophic. Increasing Mg-concentration in the p-GaN results in a reduction of the gate leakage at high forward gate bias. As a consequence, devices with higher Mg doping have long TTF (more than two orders of magnitude with respect to the samples with lower Mg doping).