Based on the STM32 dual tone mtdtifrequency signal （DTMF） detection and recognition

本文介绍了利用意法半导体公司的STM32F103RET芯片在完成液晶显示、键盘扫描、RTC等主控工作的同时,利用芯片集成外设模数转换器（ADCl）、定时器（TIM2）以及DMA等外设资源,完成对DTMF信号的采样。并使用软件算法完成自动增益控制,以及戈泽尔算法计算单音功率,根据信号的二次谐波功率,可靠迅速地检测和识别出按键信息。并深入讨论了戈泽尔算法中N值的取值范围,为自动增益控制的稳态功率值提供了依据。最后经过测试,完全满励Tu标准。     

PCM码流中MFC信号的解码

本文采用戈泽尔算法和线性调频Ｚ变换算法分析了离散ＭＦＣ信号的特征，并在高速ＤＳＰ ＴＭＳ３２０２０上用戈泽尔算法完成了ＰＣＭ码流中ＭＦＣ信号的解码，算法简单可靠，取得了令人满意的结果。     

模拟调制参数高精度测量算法研究

为了满足模拟调制信号的测试需求,提出并实现了模拟调制参数高精度测量算法。首先介绍模拟调整参数测量流程,确定模拟调制参数高精度测量算法需要完成的任务。在此基础上,提出高精度模拟调制参数测量的关键技术,着重对基于戈泽尔算法的载波频偏及载波功率测量、调制参数测量的算法进行详细的描述。另外介绍模拟调制参数高精度测量算法的实现结果。试验测试表明,模拟调制参数高精度测量算法能够很好地满足模拟调制信号的测试需求。     

基于数字AGC的控制算法

提出了一种新的数字自动增益控制(Automatic Gain Control,AGC)控制算法,这种算法弥补了AGC芯片控制范围和控制精度不满足工程要求的缺陷,解决了其他算法没有处理的问题。阐述了输入信号能量提取算法、输入信号的能量滤波算法以及控制范围和控制精度调整算法,给出了基于新算法的AGC控制过程框图,分析了输入信号能量提取算法的性能和原理,对能量滤波算法进行了仿真,并对控制范围和控制精度算法进行了设备测试和验证。     

基于基带信号包络的数字AGC设计与实现

在卫星扩频通信系统中,通常采用自动增益控制(Automatic Gain Control,AGC)技术解决大动态的信号起伏和干扰,以实现扩频信号的快速捕获和跟踪.分析了扩频接收机基带信号数字采样门限,通过用信号包络功率值作为AGC控制信号,实现了接收基带信号大动态范围的信号处理,完成了数字AGC自适应控制.利用扩频信号进行完全捕获后的包络信号作为AGE信号可以有效防止信号捕获过程中多普勒频移等引起的失锁和误捕,实现扩频接收机RF(射频)信号大动态范围的信号控制.     

RF信号功率检测模块设计

现代无线接收需要精确的RF功率管理,以实现自动增益控制等目的。利用对数放大器AD8307芯片,可以制成RF信号功率检测模块,该模块具有良好的功率检测线性度,低输出阻抗,较大的动态范围和较强的抗干扰性。     

基于Labview的短时突发信号的捕获与检测系统

讨论了短时突发信号的捕获与检测的相关技术,分析了几种相关理论算法,采用戈泽尔算法计算信号功率谱的方式替代传统FFT算法,以此改进传统的power-law检测器;结合时频分析的方法,依据软件无线电的思想建立了一个突发信号捕获与检测系统.文中给出了系统的组成及实现步骤,并对系统进行了实际测试.从测试结果看,本文提出的突发信号捕获与检测方案具有良好的性能.     

基于FPGA的大动态数控AGC系统设计

自动增益控制(AGC)是接收机的重要问题,传统模拟实现精度不高、灵活性差、调试复杂。介绍了一种大动态数控AGC实现方法,直接累加均方值估算信号功率,经对数运算后与参考值比较,得到对应需放大或缩小的功率值,通过查表再反馈控制前端,全过程由程序控制实现,执行元件为DVGA芯片AD8370。仿真及实测结果表明,该方法对信号功率变化响应迅速、控制精度较高,且适合FPGA实现,动态范围可达70dB。     

基于FPGA的中频AGC电路设计

传统数字自动增益控制（AGC）电路采用模数转换器（ADC）采集信号后进行信号处理得到幅值信息实现自动增益控制,此过程对采样速率和算法要求较高。为降低对ADC采样速率和后级信号处理算法要求,设计了一种采用高速比较器与数字器件（DAC＋FPGA/CPLD）实现的峰值检测电路,并将其应用在中频数字自动增益控制电路中,电路可以在1 MHz至60 MHz对信号进行自动增益控制,可以将峰峰值稳定在2±0.2 V范围。     

RF功率控制电路对电压幅度设定的要求

典型的现代通信信号链由发射部分和接收部分组成,这两个部分都需要RF(射频)功率监测和控制(如图1所示)。通常将RF功率监测和自动增益控制(A G C)技术相结合利用与参考电压设定值相比较的方法来监测这两部分电路中的RF功率。接收端的信号监测通常在中频(IF)完成,而发射端的功率监测可以在R F或者IF频段完成。有两种最常见的方法,一种是给控制增益链(通常在IF)增加一个可变增益放大器(VGA),另一种是通过调节功率放大器(PA)的偏置电压直接控制RF信号。在某些情况下可能采用两种方法。(Translation of Figure1)L N A=低噪声放大器P …     

一种有效的内环AGC电路

设计了一款应用于移动数字电视调谐器芯片中的数字式内环自动增益控制(Automatic Gain Control,AGC)电路。该控制电路采用的算法有效避免了死循环的问题,并且提高了AGC电路的响应时间。电路设计利用Verilog硬件描述语言进行描述,通过了功能仿真并在FPGA上进行了验证。最终采用TSMC 0.13μm CMOS工艺,完成了电路版图。芯片面积在126μm×106μm,平均功耗在3.876 mW左右。     

Digitally-controlled automatic gain control circuits for CMOS CCDcamera interface

Automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems are described. The required gain of the proposed AGC is controlled directly by digital bits. The amplifying function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the effective bandwidth of the AGC. While the three-stage prototype shows 32 dB AGC dynamic range in 1/8 dB steps, the proposed two-stage AGC reduces the power and chip area further     

A "divide and conquer" technique for implementing wide dynamic range continuous-time filters

This paper presents a technique for implementing analog filters with wide dynamic range and low power dissipation and chip area. The desired dynamic range of the filter is divided into subranges, each covered by a different filtering path optimized specifically for this subrange. This results in small admittance levels for the individual filtering paths and correspondingly small power dissipation and chip area. The system provides undisturbed output during range switching, contrary to conventional automatic gain control (AGC)/filter arrangements that generate disturbances every time the gain of the AGC changes. We also report on a low-noise highly linear CMOS transconductor useful for high-frequency applications. A chip implementing the ideas of this paper was fabricated in a 0.25-/spl mu/m digital CMOS process. The intended application of the filter is channel selection in an 802.11a/Hiperlan2 Wireless Ethernet receiver. The chip dissipates 9 mA, occupies an area of 0.7 mm/sup 2/, and maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB over a 48-dB signal range, with good blocker immunity. This performance represents at least an order of magnitude improvement over existing channel selection filters, even those that do not achieve disturbance-free operation.     

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced down-converter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.     

An analog front end for 2400-bit/s split-band full-duplex modems

An analog front-end LSI for 1200/2400 full-duplex modems which conform to CCITT V.22. and Bell 212A is described. The chip includes A/D and D/A converters, bandlimiting filters, delay equalizers, AGC circuit, tone generator, multipurpose low-pass filter, and voltage reference generator. The chip is fabricated by a 5-/spl mu/m CMOS process, and chip size is 6.50 mm/spl times/6.37 mm. The circuit operates from +5.0-V and -5.0-V power supplies. Typical power consumption is 100 mW.     

SFD-AGC algorithm with ADC digitalizing bit fully utilized and stable PAR

Aiming at making full use of analog to digital converter (ADC) digitalizing bit without oversaturation while keeping peak to average ratio (PAR) stable, this paper puts forward a new segmented full-digital (SFD)-automatic gain control (AGC) algorithm for a new long term evolution (LTE) communication system. Segmented digital gain control strategy is adopted to adjust the gain by only one step based on detected power status. Whether the gain needs to be adjusted is determined by current signal state derived from the change ranges of adjacent root mean square (RMS) of input signal, but not the difference between the power level of current signal and target signal. Software simulation and hardware implementing had been conducted with LTE frequency division dual (FDD) uplink signal and the results indicated that the proposed AGC algorithm can judge power status accurately and hence adjust the gain precisely in one step with a short delay, further, it can make full use of ADC digitalizing bit without oversaturation as well as keeping stable PAR. In addition, the mean error vector magnitude (EVM) was confined less than 1.6% to meet the 3rd generation partnership project (3GPP) standard well.     

A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

Analog AGC Circuitry for a CMOS WLAN Receiver

The IEEE 802.11a standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in multipath WLAN environments. The high peak-to-average power ratio (PAPR) of OFDM signals, along with stringent settling-time constraints, make conventional closed-loop automatic gain control (AGC) schemes impractical for WLAN receivers. In a direct conversion receiver, AGC and channel-select filtering are performed by analog baseband circuitry. A baseband signal processor using a new open-loop analog gain-control algorithm for OFDM is described. The new AGC algorithm uses switched coarse gain-setting steps followed by an analog open-loop fine gain-setting step to set the final gain of variable gain amplifiers (VGAs). The AGC was implemented in a 0.18-$muhbox m$CMOS process using newly designed circuits including linear VGAs, RMS detectors, and current-mode computation circuitry. Simulation and measurement results verify that the new AGC circuit converges with gain error less than 1dB to the desired level within 5.6$muhbox s$.     

A feed-forward AGC circuit with 48 dB-gain range, 1.2 μs minimum settling time for WiMAX receiver

The IEEE 802.16 standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in WiMAX environment. The stringent settling-time constraints of OFDM signals make conventional closed-loop feedback AGC impractical for WiMAX applications. This paper presents a novel fast-settling feed-forward automatic gain control (AGC) circuit designed for WiMAX receivers. The proposed AGC uses a switched coarse gain-setting followed by a continuous fine gain-setting to accelerate locking speed. The coarse gain-setting is performed without peak detection (PD) and the fine gain-setting is carried out by a one-step method both for shortened settling time. The chip is fabricated in 0.13 μm CMOS technology. The measurement results verify that the 48 dB AGC converges to the desired level within 1.2 μs minimum settling time. Besides, the THD is 0.32–1.37 % and the power consumption is 5.2 mW accordingly.