I-V characteristics of Schottky contacts based on quantum wires

In this paper we derive the I-V characteristics of Schottky contacts based on bulk metal to semiconductor quantum wires interfaces. The obtained results show that quantum confinement is a strong reduction of the reverse saturation current when compared to conventional Schottky contacts. Numerical simulations are carried out to highlight the advantages of using these proposed heterodimensional interfaces in applications involving low-noise photodetectors and low-leakage gate electrodes.     

Experimental and numerical analysis of channel-length-dependent electrical properties in bottom-gate,bottom-contact organic thin-film transistors with Schottky contact

Channel length dependence of field-effect mobility and source/drain parasitic resistance in pentacene thin-film transistors with a bottom-gate, bottom-contact configuration was investigated. Schottky barrier effect such as nonlinear behaviors in transistor output characteristics appeared and became more prominent for shorter channel length less than 10 μm, raising some concerns for a simple utilization of conventional parameter extraction methods. Therefore the gate-voltage-dependent hole mobility and the source/drain parasitic resistance in the pentacene transistors were evaluated with the aid of device simulation accounting for Schottky contact with a thermionic field emission model. The hole mobility in the channel region shows smaller values with shorter channel length even after removing the influence of Schottky barrier, suggesting that some disordered semiconductor layers with low carrier mobility exist near the contact electrode. This experimental data analysis with the simulation enables us to discuss and understand in detail the operation mechanism of bottom-gate, bottom-contact transistors by considering properly each process of charge carrier injection, carrier flow near the contact region, and actual channel transport.     

Simulation and fabrication of high voltage AlGaN/GaN based Schottky diodes with field plate edge termination

In this paper, we report the breakdown voltage (BV) of AlGaN/GaN based Schottky diodes with field plate edge termination. Simulation and fabrication of AlGaN/GaN Schottky diodes were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. From the simulations, it is found that for a given gate-Ohmic distance (L_gd) of 10 μm, 2DEG of 1 × 10¹³ cm⁻² and field plate length (L_FP) of 2.5 μm, highest BV can be obtained for a silicon nitride thickness of 8000 Å and this BV value is more than 5 times that for a Schottky diode without field plate. The breakdown voltages were also simulated for different field plate lengths. The BV values obtained on the fabricated Schottky diodes are compared with the simulation data and the experimental results follow the trend obtained from the simulation. Simulations were also carried out on a Schottky diode with field plate placed over a stepped insulator with L_gd = 10 μm, L_FP = 5 μm and 2DEG = 1 × 10¹³ cm⁻² and the obtained BV values are about 7 times that without field plate.     

Correlation between barrier heights and ideality factors of H-terminated Sn/p-Si(1 0 0) Schottky barrier diodes

Schottky barrier diodes (SBDs) were prepared by evaporation on H-terminated p-Si(1 0 0) surfaces. The Si(1 0 0)-H surfaces were obtained by wet chemical etching in diluted hydrofluoric acid. The current–voltage (I–V) characteristics of real SBDs are described by using two fitting parameters that are the effective barrier height (EBH) and ideality factor n. They were determined from I–V characteristics of SBDs (30 diodes) fabricated under experimentally identical conditions. The obtained values of EBHs varied from 0.729 to 0.749 eV, and the values of ideality factors varied from 1.083 to 1.119. The results showed that both parameters of SBDs differ from one diode to another even if they are identically prepared. The EBH distributions were fitted by two Gaussian distribution functions, and their mean values were found to be 0.739 ± 0.003 eV and 0.733 ± 0.001 eV, respectively. The homogeneous barrier height of SBDs was found to be 0.770 eV from the linear relationship between EBHs () and ideality factors (n).     

Fabrication and electrical characteristics of Schottky diode based on organic material

The current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of Al/Orange G/n-Si/AuSb structure were investigated at room temperature. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (BH) and the series resistance. The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions, and it was seen that there was a good agreement between series resistances from both methods. The C-V characteristics were performed at 10 kHz and 500 kHz frequencies, and C-f characteristics were performed 0.0 V, +0.4 V and −0.4 V.     

高Al组分AlGaN肖特基二极管研制

制备了高Al组分AlxGal-xN肖特基二极管(x≥0.4),并且研究了该二极管在退火前后I-V特性的变化.计算了退火前后该器件的理想因子、势垒高度.退火后势垒高度由0.995 eV提高到1.1689 eV,理想因子由1.699增大为1.934,器件的接触特性得到改善,在-5V时,暗电流密度减小为1.025×10-6 A/cm2.     

退火对Pt/TiO2肖特基二极管结构及电学性能的影响

以硅为衬底,采用射频磁控溅射技术制备了TiO2薄膜,利用扫描电子显微镜及拉曼光谱对退火前后的TiO2进行表征与结构分析.结果表明,退火后的TiO2具有良好的结晶特性,且呈锐钛矿结构.在此薄膜工艺条件下,以TiO2为半导体层在玻璃基底上制备了Al/TiO2/Pt肖特基二极管,并在153～433 K温度范围内对其进行了I-V测试,得到以下结果:在整个温度范围内,A1/TiO2/Pt肖特基二极管均表现出良好的整流特性;其理想因子随温度升高而降低,势垒高度随温度升高而升高;在433 K下,理想因子为1.31,势垒高度为0.73,表明此肖特基二极管已接近理想的肖特基二极管.     

一种指数掺杂的砷化镓平面肖特基变容二极管的设计与制作

利用标准微电子工艺研制出了一种可以应用于微波倍频电路中的肖特基势垒变容二极管,采用平面结构的制作工艺,克服了传统制作工艺的不易集成的缺点.并且在N型层的掺杂浓度呈指数规律,使变容管的变容比高于传统的均匀掺杂结构,有利于提高倍频电路的工作频率和输出功率.采用台面隔离工艺以形成分别用于制作肖特基接触和欧姆接触的两个台面.经...     

Accurate surface potential determination in Schottky diodes by the use of a correlated current and capacitance voltage measurements.Application to n-InP

Based on current voltage(I-V_g) and capacitance voltage(C-V_g) measurements,a reliable procedure is proposed to determine the effective surface potential V_d(V_g) in Schottky diodes.In the framework of thermionic emission,our analysis includes both the effect of the series resistance and the ideality factor,even voltage dependent. This technique is applied to n-type indium phosphide(n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C-V_g measurements.The study clearly shows that the depletion width and the flat band barrier height deduced from C-V_g,which are important parameters directly related to the surface potential in the semiconductor,should be estimated within our approach to obtain more reliable information.     

Si和Si尖上纳米金刚石场电子发射性质的研究

研究了Si和Si尖上纳米金刚石场电子发射性质。纳米金刚石是利用热灯丝CVD法合成的，反应气体是CH4、N2和H2的混合物。实验结果表明Si衬底上的纳米金刚石特别是Si尖上的金刚石与多晶金刚石相比，前者极大地改善了场发射性质。场发射电场阈值和电流与金刚石晶粒度密切相关。文中对其结果进行了讨论。     

The effects of the temperature and annealing on current-voltage characteristics of Ni/n-type 6H-SiC Schottky diode

The temperature dependence of current-voltage (I-V) characteristics of as-fabricated and annealed Ni/n-type 6H-SiC Schottky diode has been investigated in the temperature range of 100-500 K. The forward I-V characteristics have been analysed on the basis of standard thermionic emission theory. It has been shown that the ideality factor (n) decreases while the barrier height (Φ_b) increases with increasing temperature. The values of Φ_b and n are obtained between 0.65-1.25 eV and 1.70-1.16 for as-fabricated and 0.74-1.70 eV and 1.84-1.19 for annealed diode in the temperature range of 100-500 K, respectively. The I-V characteristics of the diode showed an increase in the Schottky barrier height, along with a reduction of the device leakage current by annealing the diode at 973 K for 2 min.     

(NH4)2S treatment of the Si (100) surface and its effects on Al/Si Schottky barrier heights

ates originating from dangling bonds are passivated with S atoms.     

Si (100) 表面 (NH4)2S 处理及其对Al/Si肖特基势垒的影响

The effect of Si （100） surface S passivation was investigated. A thick film with a high roughness value was formed on the Si surface treated by （NH4）2S solution, which was attributed to physical adsorption of S atoms. SEM and XPS analyses reveal that Si surface atoms were chemically bonded with S atoms after Si surface treatment in NH4OH and （NH4）2S mixing solution. This induces a more ideal value for the Schottky barrier height compared with a diode treated only by HF solution, indicating that surface states originating from dangling bonds are passivated with S atoms.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Capacitance-Voltage characteristics of metal-insulator-semiconductor diodes with S passivation and Si interface control layers on GaAs and InP

GaAs and InP surfaces have been prepared by gas-phase and liquid-phase polysulfide passivation techniques followed by the deposition of Si interface control layers (ICLs) by e-beam evaporation. For GaAs surfaces, the performance of an ICL consisting of 1.5 nm Si on top of 0.5 nm of Ge has also been evaluated. Metal-insulator-semiconductor diodes with aluminum top electrodes were fabricated on these surfaces using silicon nitride deposited by a remote plasma-enhanced chemical vapor technique or silicon dioxide deposited by a conventional direct plasma-enhanced chemical vapor deposition technique. The quality of the interfaces was analyzed by capacitance-voltage (C-V) measurements and the interface state densities D_it were deduced from the C-V data using the high-low method. Values as low as 1.5 × 10¹² eV⁻¹cm⁻² were obtained for polysulfide-passivated GaAs surfaces with a Ge-Si or Si ICL, the lowest ever demonstrated using the high-low method for an ex-situ technique not involving GaAs epitaxy. For InP, the Si ICL does not reduce D_it below that of 2 × 10¹² eV⁻¹ cm ⁻² that was obtained for the polysulfide passivated surface. The Si ICL produces an interface that degrades more slowly on exposure to air for both GaAs and InP.     

Effect of Si or Al interface layers on the properties of Ta and Mo contacts to p-type SiC

We present our results on the role of Si or Al interface layers on the structure and electrical properties of tantalum and molybdenum contacts to p-type 6H-SiC. Thin films of Ta or Mo were deposited on p-type SiC with and without p-doped Si or Al interface layers. The Ta/p-SiC, Ta/p-Si/p-SiC, Ta/Al/p-SiC, Mo/p-SiC, and Mo/Al/p-SiC structures were annealed at high temperatures up to 1200°C using the rapid thermal annealing process, in Ar-H₂ or N₂-H₂ ambient. X-ray diffraction analysis showed TaSi₂ in both Ta/p-SiC and Ta/p-Si/p-SiC structures annealed in Ar-H₂ ambient. For the N₂-H₂ ambient anneal tantalum nitride (TaN) was formed in Ta/p-SiC and Ta/Al/p-SiC, and TaN plus TaSi₂ in Ta/p-Si/p-SiC. While there was evidence of interaction between Mo and Si or Al no intermetallic phases were observed. Electrical measurements revealed that both TaN in Ta/p-SiC and TaN + TaSi₂ in Ta/p-Si/p-SiC structures made ohmic contacts, with specific contact resistances of about 2.13 × 10⁻³ and 1.47 × 10⁻¹ Ω-cm², respectively. The specific contact resistance for Ta/Al and Mo/Al layers on p-SiC decreases with increasing temperature and varies with anneal ambient. The values calculated for Ta/Al/p-SiC and Mo/Al/p-SiC were about 4.22 × 10⁻⁴ at 1100°C and 4.5 × 10⁻⁵ Ω-cm² at 1200°C, respectively. The heavy surface doping provided by Al in Ta/Al/p-SiC and Mo/Al/p-SiC is responsible for the low specific contact resistance.     

Effect of bump characteristics and temperature variation on the online contact resistance of anisotropic conductive joints

Anisotropic conductive film (ACF) suffers a major drawback in regard to reliability even though it has merits, such as reduction in interconnection distance, high performance, and environmental friendliness. The factor of thermal warpage may lead to a highly unreliable electrical connection in the assembly. The work presented in this paper focuses on the online contact-resistance behavior of the ACF joint during thermal shock and compares the results of two different types of dies (Au/Ni bump and bumpless). For this work, we used a flip chip of 11 × 3 mm² in dimension. The flex substrate used was made of polyimide film with an Au/Ni/Cu electrode and daisy-chained circuit for a matching die-bump pattern. The ACF that was used is an epoxy resin in which nickel and gold-coated polymer balls are dispersed. Tests for three different thermal-cycling profiles (125°C to −55°C, 140°C to −40°C, and 150°C to −65°C) were carried out. The samples bonded at a temperature of 180°C, and a pressure of 80 N was used. The initial contact resistances of Au/Ni bump and bumpless samples were 0.25 ω and 0.4 ω respectively. A comparative study was carried out from the results obtained. The results showed that for the flip-chip-on-flex (FCOF) packages having an Au/Ni bump, the increase in online contact resistance is higher than that of the FCOF packages having bumpless chips. For example, in the thermal-cycling profile of 140°C to −40°C, the online contact resistance for the Au/Ni bump raised to 4.6 ω after 180 cycles, whereas it was only 1.3 ω for the bumpless sample. The bump height and bump materials were found to be the main factor for such variation. Results show that, above the glass-transition temperature (T_g), the ACF matrix becomes less viscous, which reduces its adhesive strength and lets the higher bump height of the chip result in a higher standoff of the package and thus sliding is easier to take place. The responses by the assemblies in hot and cold conditions are examined, and in-chamber behavior of the assembly is studied and explained.     

Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.