基于ARM和FPGA的SiP系统级封装设计

介绍了系统级封装的概念和特性,阐述了SiP设计的关键技术和基本生产实现流程。设计了一款基于ARM和FPGA管芯的SiP通用微处理系统,介绍了该SiP系统的整体框图,并详细分析了系统各部分电路的功能结构。该系统具有体积小、功耗低及功能完备等优点,充分展现了SiP技术的优越性。     

MEMS陀螺芯片的晶圆级真空封装

微机电系统(MEMS)陀螺需要真空封装以确保其检测精度,晶圆级真空封装可以使MEMS微结构避免芯片切割过程中的粘连以及颗粒污染,提高芯片的成品率.为实现MEMS陀螺芯片的晶圆级真空封装,提出了一种全硅MEMS陀螺芯片的晶圆级真空封装结构方案,并突破了Si-SiO2直接键合、吸气剂制备、金—硅(Au-Si)键合等关键技术...     

基于半桥MOSFET芯片铜带夹扣堆叠的电源SiP设计

采用系统级封装（System in Package,SiP）设计是实现电源小型化的有效方式之一。同步BUCK DC-DC变换器中的半桥功率开关MOSFET,通过堆叠工艺利用纵向空间,将芯片的占用面积降低了36%。MOSFET芯片表面做焊锡浸润材料金属化处理,直接与铜带夹扣锡膏烧焊,将电流路径电阻减小了约10倍,同时热传导效率得到了改善。通过多芯片微组装工艺,将电源控制器、MOSFET芯片、电感器及其他必要器件集成在BGA陶瓷封装内。研制的电源SiP样机尺寸为20 mm×18 mm×4.8 mm,可双通道独立输出15 A,或双通道并联输出30 A电流,电源转换效率达93%以上。     

新型埋入式板级封装技术

越来越多的高密度、多功能和小型化需求给封装和基板都带来了新的挑战,很多新的封装技术也应运而生,包括引起众多关注的埋入式封装技术.在本文中,我们首先对埋入封装技术的优势、挑战以及发展现状进行了介绍.然后通过将功能性有源器件埋入到有机基板中的尝试说明了设计、制造和测试埋入式封装这一新兴技术的可行性.制定一个切实可行的解决方案,有利于降低制造成本和市场的产品开发周期.我们提出的这种埋入式板级封装技术,与传统的封装和基板工艺都兼容.此外,本文设计了将功能性的MOSFET有源芯片埋入到有机基板中的板级封装模块结构,对该模块进行了热机械仿真分析,找到了最大应力点,优化了工艺设计.最后,结合传统的基板工艺,制备了埋入式板级封装样品,并完成了埋入式板级封装模块的电阻通断测试和功能测试,验证了该工艺设计的可行性.     

微机电系统的封装技术

MEMS封装是在微电子封装技术基础上发展起来的一项关键的MEMS技术。介绍了MEMS封装技术的功能、特点与分类。在此基础上,重点介绍了键合技术、上下球栅阵列技术、倒装芯片技术、多芯片技术以及3-D技术等几种重要的MEMS封装技术。最后,进一步探讨了MEMS封装的发展趋势及研究方向。     

TO-252封装电磁仿真分析

随着工艺尺寸的缩小和工作频率提高,表面贴片式封装技术中的PCB板和键合线都可能对电路的电气特性产生影响,因此有必要对这种封装技术进行信号完整性的分析。文章介绍了一种表面贴片封装TO-252,采用3D电磁仿真软件HFSS进行建模,分析仿真PCB板材、厚度和键合线的长度、拱高、根数及键合线间的距离对封装设计中信号传输的影响,为实物封装设计起指导作用。     

WCDMA系统级仿真技术与接入控制仿真研究

介绍了系统级仿真技术的特点和工作流程，分析了基于OPNET网络仿真软件的WCDMA系统建模方法，并以一种改进的接入控制算法为例，实现了在该WCDMA系统级仿真平台上的仿真。     

基于圆片级阳极键合封装的高g_n值压阻式微加速度计

设计了一种适合于高gn值压阻式微加速度计圆片级封装的结构,解决了芯片制造工艺过程中电极通道建立、焊盘保护、精确划片等关键技术。采用玻璃—硅—玻璃三层阳极键合的方式进行圆片级封装,较好地解决了芯片密封性、小型化和批量化等生产难题。在4 in生产线上制作的高gn值压阻式微加速度计样品,尺寸仅为1 mm×1 mm×0.8 mm;对传感器进行的校准与抗冲击性能测试,结果表明:样品具备105gn的抗冲击能力、0.15μV/gn/V的灵敏度以及200 kHz的谐振频率。     

Chiplet封装结构与通信结构综述

近年来,随着摩尔定律逼近极限,片上系统(system on chip, SoC)的发展已经遇到瓶颈.集成更多的功能单元和更大的片上存储使得芯片面积急剧增大,导致芯片良品率降低,进而增加了成本.各大研究机构和芯片制造厂商开始寻求使用先进的连接和封装技术,将原先的芯片拆成多个体积更小、产量更高且更具成本效益的小芯片(Chiplet)再封装起来,这种封装技术类似于芯片的系统级封装(system in package, SiP).目前Chiplet的封装方式没有统一的标准,可行的方案有通过硅桥进行芯片的拼接或是通过中介层进行芯片的连接等,按照封装结构可以分为2D,2.5D,3D.通过归纳整理目前已发布的小芯片产品,讨论了各个结构的优缺点.除此之外,多个小芯片之间的通信结构也是研究的重点,传统的总线或者片上网络(network on chip, NoC)在Chiplet上如何实现,总结遇到的挑战和现有解决方案.最后通过对现有技术的讨论,探索以后小芯片发展的趋势和方向.     

Impact on retail checkout ergonomics of scanner technology evolution and package design

The design of bar code scanners has steadily improved scanning performances over the past 20 years. Changes in scan patterns, improvements in decode algorithms, and design features of the hardware user interface have resulted in scanners that are ergonomically superior both in biomechanics and overall performance. This study reviewed scanner performance and technological developments, and compare these to changes in checkstand use and the mix of merchandise packages scanned. The results indicate that the impact of future innovations in scanner design to improve throughput and the accuracy of data captured will be minimal. The greatest challenge to improve overall checkout performance is for merchandise suppliers to consider the ergonomics of scanning merchandise based on package design and placement of the bar code.

Relevance to industry

This work shows the impact of scanner design on cashier productivity in the retail checkout environment. Improvements in the user interface of scanners and the scanner optical recognition logic has shown a dramatic impact on the total percentage of scanned items. Package design and bar code placement is the next area to enhance the ergonomics of scanning.     

支持Modelica模型的半物理仿真系统设计及关键技术

针对当前基于MATLAB/SIMULINK的半物理仿真（Hardware in Loop Simulation,HILS）系统中不支持多领域建模、联合仿真模型转换过程复杂且存在误差等问题,提出基于Modelica和建模仿真软件MWorks进行HILS的方法,分析其所涉及的建模方法、实时仿真接口和代码生成等关键技术,并以此为基础构建支持Modelica模型的HILS.以前起落架转向系统和起落架收放系统为应用实例,建立HILS平台,对该方法进行验证.仿真结果表明该方法可行,结果可信度高.     

A standard Pascal event simulation package

A package implemented using standard Pascal is described. It provides the user with basic tools for discrete event-orientated simulation, and includes facilities for scheduling and causing pending events, handling of LIFO and FIFO queues, control of periodical dumping of statistics and comprehensive initialization and error routines. Two versions of the package have been implemented, using tree and linked list structures for scheduled events. Their relative performances are compared. The tree structure proves to be more efficient except in the minority of cases where the set of scheduled events has to be searched frequently; it also provides a much more efficient scheduling algorithm than does a linked list structure. This package is primarily intended as a communication network design tool, and a simple example of this type of usage is included. It could also be used in undergraduate teaching. Coding examples are given for the main procedures, in the two implementations.     

基于EDA仿真技术的电子时钟系统设计

介绍EDA技术的特点以及设计流程,强调EDA仿真技术在现代电子系统的重要地位及作用。以modelsim和quartus2为平台,采用自顶向下分层次、模块化的设计方法,设计了一个带整点报时和星期计数器的电子时钟控制电路,从中可体现出数字系统的硬件设计向软件化方向发展的新思路。     

Suitability of using microcontrollers in implementing new P-system communications architectures

The distributed implementation of P-Systems has met with the communications bottleneck problem. When the number of membranes grows in the system, the network gets congested and the times to execute an evolution step degrade. Several published analysis have proved that there is a very strong relationship between communication time and evolution rules application time in membranes of the system. Moreover, recent works present analysis for distributed architectures that are technology independent, based on: allocation of several membranes in the same processor; the use of proxies for communication among processors; and, token passing in the communication. These solutions avoid communication collisions, and reduce the number and length for communication among membranes. All these facts allow to obtain a better evolution time than in others suggested architectures which they get congested quickly by network collisions when the number of membranes grows. The aim of this work is to do an extrapolation of the communications architectures denominated “partially parallel evolution with partially parallel communication“, to analyze their suitability to be implemented using a low cost universal membrane hardware/software component based on microcontrollers. This work was presented in part at the 13th International Symposium on Artificial Life and Robotics, Oita, Japan, January 31–February 2, 2008     

地震物理模拟系统设计技术

地震物理模拟系统主要由定位系统和数据采集系统组成。定位系统设计开发中应用FPGA可编程器件,实现了对光栅返回脉冲的噪声信号处理,可靠计数、锁存和同步信号的实时触发功能。采集系统采用USB2.0技术,实现对模拟地震数据的高速采集传输。     

The design of a terminal independent package

Chareacter-mapped display terminals very considerably. TIP is a Terminal Independent Package which conceals the details of efficiently handling terminal protocols from applications programs. There is a conflict between the ability to handle esoteric terminal features and providing a uniform programmer's interface for all terminals. This paper discusses the conflicts and the design approch which resolved them.     

ZigBee技术在智能箱式变电站中的应用

简单分析了现有箱式变电站中存在的技术问题,介绍了ZigBee技术的特点和优势。将ZigBee技术应用于箱式变电站,给出了无线通讯技术的硬件电路和软件方案,设计了基于ZigBee技术的智能箱式变电站。根据所设计的变电站配电运行表明,将无线ZigBee技术应用于箱式变电站,可以实现箱式变电站的智能化,同时该变电站还具有低成本、低功耗、实时性及可靠性高等特点。