封装引线框架产业大有可为

本文叙述了半导体封装产业发展趋势及市场前景,同时指出了封装引线框架面临的良好市 场前景,我国的引线框架业将会大有作为。     

IC封装用铜合金引线框架及材料

本文评述了国内外IC封装用铜合金引线框架及材料的研发现状,主要涉及封装对引线框架材料的要求,铜合金引线框架材料的特性,铜合金引线框架材料研发动态,引线框架的制作技术以及市场需求等内容,并由此分析它们的发展趋势。     

芯片封装引线框架的应用及市场

集成电路IC半导体产业的制造流程被分为芯片制作前工序和芯片封装测试后工序两大生产系统。封装起到保护芯片、重新分布输入／输出I／O获得更易于装配处理的引脚节距．为芯片提供良好散热通路．便于测试和老化试验等极其重要作用。IC封装有许多种板结构尺寸、外形和引脚数量．以满足各类IC发展和系统的不同要求。IC封装两个主要基本结构类别为引线框架式封装和基式封装，前是一类十分重要而技术悠久的封装，采用引线框架的产品类型仍在半导体产业中占据主导地位。     

建立封装芯片热阻网络模型的方法研究

针对电子设备系统级热分析中封装芯片模型复杂程度与计算精度的矛盾,引入热阻网络法,替代系统级分析中封装芯片的详细物理模型;并以某PBGA封装芯片为例,进行两种建模方法的对比分析,同时介绍一种快速确定网络中热阻值的方法.结果表明,热阻网络等效方法具有模型简单、分析快速、准确度高的优点,在系统级热分析中可完全替代详细的物理模型.     

芯片封装引线电性能的测试

随着集成电路的高速化、高集成化、高密度化封装的发展，封装引线的电性能对集成电路的影响越来越大，封装引线电性能的测试与控制也越显重要。     

新型引线框架封装集成QFN、TQFP

Amkor最近推出了“整合四边封装技术”,这是一种基于引线框架的塑料封装技术平台,融合了无引线四边扁平封装（QFN）和薄四边扁平封装（TQFP）两种技术。有趣的是,这种方法消除了过去外围引线结构的引脚数限制,可将标准引线框架封装的外围I／O接口数增大两倍,接近400个分离引脚——同时,对于特定的引脚数,该方法也缩减了50％的封装面积。其基本思想是,将标准外围引线有选择地与一排或两排内部焊盘相结合。     

集成电路陶瓷封装热阻RT—JC的有限元分析

给出了采用热测试芯片的三类陶瓷封装的结到外壳热阻ＲＴ－ＪＣ的有限元模拟结果，并与测量结果进行了对比。讨论了芯片和上壳的温度分布，导热脂层对壳温分布和测量的影响。还模拟了ＲＴ－ＪＣ与芯片厚度，芯片面积，芯片粘接层热导率的关系。     

晶圆级封装的优化散热分析

通过有限元分析软件ANSYS,对一款晶圆级封装的产品进行有限元分析仿真,讨论了空气对流系数、环境温度、基板厚度、焊球间距等因素对芯片热阻的影响。结果表明:考虑成本、散热等综合因素,选择空气对流系数为25×10–6W/(mm·℃)基板厚度为0.10 mm、焊球间距为0.5 mm为最优参数,可满足实际生产需要。     

框架有效成本与内引线长度技术能力的关系

引线框架封装和基板封装是集成电路封装两个基本结构类别,在当前的半导体封装产业中,引线框架封装依然占据了主导地位。近年来随着有色金属价格的飞涨,对框架类产品造成了严峻的成本挑战,而通过技术手段来降低产品有效成本才是最安全、可行的方向。文章通过对框架内引线长度技术能力的差异比较,在金丝价格飞涨的情况下,发现其对框架有效成本...     

Multi-LED package design, fabrication and thermal analysis

An ultra-thin multi-LED package is designed,manufactured and its thermal performance is characterized. The objective of this study is to develop an efficient thermal modelling approach for this system which can be used for optimization of the thermal-performance of future ultra-thin designs.A high-resolution thermal imaging camera and thermocouples were used to measure the temperature distribution of the multi-LED package and the LED-die temperature for different operating powers.Finally,we compare the thermal measurements with the finite element simulation results.It is concluded that the modelling approach can assist in the thermal optimization of future multi-LED package designs.     

Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package

An ultra-miniature interconnect (IC) package such as a chip-scale package (CSP) provides a difficult challenge in electrical model extraction, particularly to multi-GHz frequencies, because the very small parasitics can easily be swamped by test fixture parasitics and/or by small measurement errors that might be negligible in a larger package. Incomplete data for the high-frequency electrical properties of package materials and small dimensional errors in physical model entry into electromagnetic (EM) simulators, again negligible in larger packages, may also cause significant error. Therefore, for ultra-miniature packages it is necessary to cross-correlate multiple measurement and simulation methods to ensure that an accurate package electrical model is obtained. This paper therefore presents a closed-loop cross-correlation of s-parameter and time domain reflectometry (TDR) measurements with EM simulation and TDR simulation for a 16-pin lead frame chip-scale package (LFCSP) and the extraction of a cross-verified electrical model to 10 GHz. The authors are not aware of the previous application of these multiple techniques to a CSP to this bandwidth.     

Transient thermal analysis of an ACF package assembly process

Transient thermal simulation was performed to analyze thermal response of the assembly process for a package using anisotropic conductive film (ACF). The main purpose of the study is to simulate the actual assembly and manufacturing process, in order to provide a first-hand approximation and insight of the thermal behavior of the package and ACF film during the process. Two assembly processes were modeled: a simplified process where the package was fixed at two different temperatures during assembly, and a detailed process where the package experienced a ramping heating process, followed by a constant temperature curing process. A full convection-conduction case was conducted first. The results indicate a weak hydrodynamic field and radiation effects, hence for computational purposes (reduced CPU time), it was decided to model the process using a conduction-only investigation. Results from the detailed process modeling indicated that during the initial ramping, within 0.02 s, the die and nozzle head experienced a small temperature drop due to the cooling effect of the ACF material and substrate. The ACF material also displayed a steep increase in temperature after contacting the die, followed by a short decay, then ramped up again. At the end of the 10-s ramping process, the ACF reached a temperature of almost 203°C, while the die was at 206°C. During the 5 s of curing, all parts reached steady state in less than 2 s     

高功耗2.5D封装的热性能优化设计分析

Based on ANSYS and Icepak softwares, the numerical analysis method is used to build up the thermal analysis model of the 2.5D package, which contains a high power CPU chip. The focus of the research is on the determination of the contributing factors and their effects on the thermal resistance and heat distribution of the package. The parametric analysis illustrates that the substrate conductivity, TIM conductivity and fin height are more crucial for heat conduction in the package. Furthermore, these major parameters are compared and analyzed by orthogonal tests, and the optimal solution for 2.5D integration is proposed. The factors' influence patterns on thermal resistance, obtained in this article, could be utilized as a thermal design reference.     

Measurement of thermal resistance of first-level Cu substrate used in high-power multi-chips LED package

The thermal resistance of the first-level Cu dissipation substrate (R_Cu) with different Cu thickness is investigated in this work. Using the “constant-forward-voltage” method, the thermal resistances of the first-level Cu dissipation substrates (R_Cu) were measured against different Cu thickness. In the initial increase in the Cu thickness (up to 0.6 mm), R_Cu decreases with the Cu thickness. As the Cu thickness over 0.6 mm, R_Cu starts to slightly increase with the Cu thickness. The thermal resistance (R_Cu) of the Cu substrate is composed of the z-direction thermal resistance (R_z) and the two-dimensional horizontal spreading resistance (R_s). The initial decrease in R_Cu should attribute to the decrease in R_s with the Cu thickness. After the initial increase in R_Cu, the R_Cu would increase and be dominated by the R_z increase with the Cu thickness. Intriguingly, a minimum R_Cu value occurs at the Cu thickness of about 0.6 mm. Also, in this paper, we discuss the possible inaccuracy factors of the “constant-forward-voltage” method.     

面向引线框架缺陷的图像配准算法

为了降低引线框架缺陷识别的误检率,比较了基于灰度的模板匹配和基于特征的匹配算法之间的优缺点,并针对引线框架缺陷检测中参考图和检测图存在差异的特点,提出基于区域定位和不变矩的特征匹配算法。该算法通过边缘检测定位出特征区域,并用不变矩进行区域特征描述。在缺陷识别试验中,相比于模板匹配算法,该算法表现出更快的结算速度,更高的配准精度,更低的配准失败概率。结果表明,该配准算法适用于引线框架缺陷识别,降低误检率。     

红外探测器封装结构电学框架设计方法

随着红外焦平面探测器的广泛应用,其封装结构朝着几个方向发展,一方面是单片小型化轻量化结构,另外一方面是多片超大规模拼接结构,无论哪种结构都需要进行封装结构的电学框架设计。文章首先列举几种可用于电学框架加工的材料,并从热应力、加工工艺水平以及电学参数方面进行比较;然后结合目前探测器规模、封装结构,以及应用给出电学框架加工材料和工艺在设计中的选取建议;最后介绍电学框架布线设计方法及注意事项。     

Fast convolution based thermal model for 3D-ICs: Methodology,accuracy analysis and package impact

Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging. Computationally fast thermal models (FTMs) are being developed for fast evaluation of the temperature distribution in 3D packages. The steady state FTM discussed in this paper is based on Green׳s function theory and exploits convolution and the fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. However, this methodology is not directly applicable for finite dimensional structures. The method of images is exploited to include the effect of insulating lateral boundary conditions. The number of images needed to ensure accurate results depends on the specific structure of the stack. A fast method to compute it is proposed together with a short analysis of its dependence on some system parameters. A two dies stack case study is thermally analyzed showing good agreement with the finite element method (FEM) results (errors less than 0.5%). The computational time is also discussed indicating a $O(N\log N)$ behavior, where N is the number of elements in the extended power maps, which include images, as well as a 70 times speed up with respect to FEM. Finally, since in the FTM the package is implicitly included in the boundary conditions, the thermal impact of its real configuration is investigated.     

集成电路塑封中引线框架使用要求

本文讲述了引线框架的主要特性以及引线框架对封装的影响,提出了一些改进方法。     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。