Design issues and insights for low-voltage high-density SOI DRAM

A physics-based study of floating-body effects on the operation of SOI DRAM is described. The study, which is based on device and circuit simulations using a physical SOI MOSFET model calibrated to an actual partially-depleted (PD) SOI DRAM technology, addresses the performance of the peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the data storage cell. Design insight for low-voltage high-density SOI DRAM is attained. Double cell design is shown to yield a dynamic retention time long enough for gigabit memories, and crude body-source ties for nMOS, with pMOS bodies floating, are shown to effectively suppress instabilities in the sense amplifier     

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM

An 8 Mb embedded DRAM has been developed. The salient feature of this embedded DRAM is page fault tolerance. Accessing across different pages can be performed using a minimum column cycle. This feature is achieved by placing a data latch and a transfer gate between the bit line sense amplifier and the column select gate. This DRAM can be reconfigured as separated 2 Mb units when it is embedded as a macro cell of an ASIC library     

Design methodology of embedded DRAM with virtual-socketarchitecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-μm design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.     

A circuit design to suppress asymmetrical characteristics inhigh-density DRAM sense amplifiers

A circuit design technique for suppressing asymmetrical characteristics in a high-density DRAM sense amplifier is discussed, and the effect of drain current imbalances between transistor pairs and the sensitivity of the sense amplifier are studied experimentally. A sense amplifier composed of parallel transistor pairs which have a reversed source and drain arrangement on a wafer is capable of suppressing the asymmetry effects to less than 15 mV in a range of submicrometer gate lengths and of reducing the layout area by about 43% compared with the conventional sense amplifier     

A 1.0-V 230-MHz column access embedded DRAM for portable MPEGapplications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm² and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented     

一种新型的SOI灵敏放大器

本文利用"灵巧的体接触(Smart-Body-Contact)"技术设计出一种新型的SOI灵敏放大器.采用Hspice软件对体硅的和新型的交叉耦合灵敏放大器进行模拟和比较,发现新型的交叉耦合灵敏放大器比体硅的交叉耦合灵敏放大器延迟时间缩短30%,最小电压分辨可达0.05V.最后,我们成功地将该电路应用于CMOS/SOI 64Kb SRAM电路,电路存取时间仅40ns.     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time andmemory-cell area efficiency of 33%

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage     

A four megabit Dynamic Systolic Associative Memory chip

A Dynamic Random Access Memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (1024×4096) associative memory chip based on a 4 Mbit DRAM, the 6 transistors per sense amplifier in a DRAM are expanded by 9 transistors per sense amplifier in the modified chip. The chip size is only slightly increased, and it is manufactured using the same processes, in the same plant, as a DRAM chip; thus should cost about the same as a DRAM. A large array of such modified DRAMs could store a terabit database and search all of it every 60 microseconds. Bit pattern searching and search-rewrite algorithms could be economically performed over very large amounts of data. The concepts and the design of the simple modified DRAM will be discussed in the paper.     

A configurable DRAM macro design for 2112 derivative organizationsto be synthesized using a memory generator

This paper describes a DRAM macro design from which 2112 configurations up to 32 Mb can be synthesized using a memory generator. The memory generator automatically creates the layout of a DRAM macro in accordance with specification inputs such as memory capacity, address count, bank count, and I/O bits count. An expandable floor layout scheme achieves the macro size comparable to that of handicraft-designed DRAM. The memory generator can customize a configurable redundancy scheme for various macro configurations. Unified testing circuits make it possible to test DRAM macros with more than 500 interface pins in a direct-memory-access mode with 33 test pads. Up to four macros on the same chip can be tested with them. Test chips with 4-Mb DRAM and with 20-Mb DRAM fabricated with 0.35-μm technology showed 150-MHz operation     

An access-sequence control scheme to enhance random-accessperformance of embedded DRAM's

An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAM's. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for regular access in graphics applications. In this paper, we propose an access-sequence control scheme which enhances the random-access performance of embedded DRAMs. Access ID numbers, an access queue register, and a write-data buffer combined with the multibank DRAM enable out-of-sequence access which reduces the page-miss penalty during random access. In the case of four successive accesses, the estimated total access time was, respectively, reduced by up to 38 and 32% for one and two page misses, and for five successive accesses with one or two page misses, it was, respectively, reduced by up to 44 and 45%     

Offset compensating bit-line sensing scheme for high density DRAM's

This paper describes a new bit-line sensing scheme that minimizes the sensitivity degradation caused by the electrical imbalance in a sense amplifier composed of scaled-down transistors. The new sensing scheme incorporates an offset compensating technique in a direct bit-line sensing scheme using a current-mirror differential amplifier. The compensation is performed by means of a simple negative feedback method that accomplishes cancellation of the total electrical imbalance in the sense amplifier with a short presetting time. The features of the circuit have been examined using simple DRAM test chips fabricated with a 0.5 μm CMOS process. Experimental results indicate that the magnitude of the imbalance of the sense amplifier is reduced to one-sixth by introducing the offset compensating scheme as compared to the conventional sensing scheme     

Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node

Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits     

An 8-ns random cycle embedded RAM macro with dual-port interleavedDRAM architecture (D2RAM)

A novel fast random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²RAM) has been developed. The macro exploits three key circuit techniques: dual-port interleaved DRAM architecture, two-stage pipelined circuit operation, and write before sensing. Random cycle time of 8 ns under worst-case conditions has been confirmed with a 0.25-μm embedded DRAM test chip. This is six times faster than conventional DRAM     

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integratedmedia chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm² /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule     

A compact thermal noise model for the investigation of soft errorrates in MOS VLSI digital circuits

A compact VLSI MOSFET model that includes an integrated thermal noise model and a methodology for the analysis of the effects of thermal noise on the performance and error rates of digital integrated circuits is presented. The usefulness of the model and methodology is demonstrated by comparing simulation results for signal-to-noise ratio to analytic results for the balanced bit-line architecture of the single-device DRAM and the associated cross-coupled pair sense amplifier. The design options and tradeoffs related to thermal noise are introduced for both the balanced bit lines and the sense amplifier are considered. The error rate as a function of signal-to-noise ratio is determined, and possible limits to DRAM construction due to inherent thermal noise are highlighted     

A high-speed clamped bit-line current-mode sense amplifier

A clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. This is achieved by relocating the large bit-line capacitance to a node within the sense amplifier that has only a minimal effect on the speed of the circuit. Bit-line clamping also minimizes inter-bit-line voltage noise coupling     

A novel circuit technology with surrounding gate transistors(SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V_cc margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL