Cascaded Diophantine Frequency Synthesis

Cascaded diophantine frequency synthesis (CDFS) is an approach to high-resolution frequency synthesis based on the mathematical properties of integer numbers and diophantine equations. CDFS can be implemented using two or more phase-locked loops (PLLs) and frequency mixing stages in a cascade topology. CDFS achieves frequency resolution arbitrarily finer than that of the constituent PLLs while maintaining their loop bandwidths and frequency hopping agility. CDFS results in intermediate signals with minimal frequency ranges in all frequency mixing stages, allowing for improved spectral purity and lower design complexity compared to the parallel form of its predecessor, diophantine frequency synthesis (DFS). CDFS architectures are modularly structured and expandable. The paper introduces CDFS focusing on the mathematical and algorithmic aspects.     

Spur-Suppression Techniques for Frequency Synthesizers

A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 mum CMOS technology. The chip area is 1.3 mm times 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 mus within 20 ppm of the target frequency.     

C频段频率合成器设计

DDS与PLL的组合方式通常有两种,PLL内插DDS和DDS激励PLL的组合方式。本文充分利用了这两种方式的优点,实现了一种能完全覆盖C频段的宽带低相位噪声频率合成源设计。首先在理论分析的基础上给出了设计方案,然后对其可行性进行了论证,最后用实验结果证明了该方案的正确性。     

小数分频频率综合器研究

针对整数分频频率合成方法存在的局限性,提出了采用小数分频频率合成的方法,分析了小数分频频率合成的实现方法,并针对其中的Σ-△调制技术的各种实现结构进行了分析和仿真,比较了各种实现方法的优劣以及∑-△调制技术中各种结构的性能优劣.在此基础上,进行了整数分频和小数分频频率合成电路实验研究,实验结果验证了小数分频频率合成的优化性能.     

小数分频频率合成器的设计

采用Σ-Δ调制小数分频器设计的频率合成器与传统的PLL(锁相环)频率合成器相比具有明显的优越性,它可以提供宽的频率范围、极高的频率分辨率、低的单边带相位噪声以及良好的杂散性能.介绍了利用该技术实现的小数分频频率合成器的原理和设计,并给出了设计结果.     

一种应用于GSM接收机频率合成器的多模分频器

介绍了一个多模分频器的设计。为了提高工作速度,采用吞脉冲(pulse-swallow)结构,并且两个计数器均采用改进的检测与置数逻辑;但经过分析,发现在吞脉冲结构下,采用该改进逻辑会存在时序问题。文章提出一种解决方法。经SpectreRF模拟,在SMIC 0.18μm CMOS工艺条件下,最高工作频率可达3.7 GHz,消耗电流1.4 mA,芯片版图面积150μm×130μm。     

A Novel Low Power Architecture for DLL-Based Frequency Synthesizers

This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13 μm CMOS technology. This fractional DLL-based frequency synthesizer is adopted for 176 MHz to 216 MHz with maximum power consumption of 2.62 mW and RMS jitter of 10 ps @ 216 MHz.     

A Review of SAW-Based Direct Frequency Synthesizers

Many new electronic systems, including spread spectrum links, require frequency synthesizers capable of providing accurate signals of high spectral purity, and must be able to change frequencies in fractions of a microsecond. Three such synthesizers based on comb generators, SAW filterbanks, and fast switches are reviewed. Each of these synthesizers can provide an output at approximately 1.3 GHz from one of over 200 frequencies of integral megahertz value.     

快速锁定、宽带双环路频率综合器的数字粗调环路

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

基于FM接收机的可变带宽频率综合器设计

本文介绍了应用在单芯片FM接收系统中可变带宽频率综合器的设计.通过同时改变电荷泵电流和滤波器的结构使锁相环的带宽发生变化,这样在不影响噪声性能(phase jitter)的前提下,锁定时间显著减小.在大电流状态下,环路带宽比锁定状态下提高了4.6倍.电路设计是采用0.6μm BICMOS工艺,仿真结果显示,在3V的电源电压下,锁定时VCO纹波电压小于0.2mV,功耗大约12mW.     

A Quadrature Modulation Transmitter Using Two Frequency Synthesizers

This brief analyzes a novel quadrature modulation transmitter architecture. The proposed architecture consists of only two frequency synthesizers, thereby reducing the RF and analog components such as RF mixer, analog filter, and digital-to-analog converter. Simulation results show that the bit-error rate and the spectral efficiency of the proposed method are close to those of conventional quadrature modulation scheme. The quadrature modulation transmitter can be implemented fully digitally through the proposed architecture if the all-digital frequency synthesizer is used. [All rights reserved Elsevier].     

基于AD9901设计的高速频率合成器

介绍了一种基于Analog Devices公司生产的新型超高速鉴相器AD9901的跳频通信用高速频率合成器的设计方案和该方案所具有的提高频率合成器频率转换速度的特点，还详细介绍了该频率合成器的工作原理，并对它的主要性能参数进行了分析。     

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13$ muhbox{m}$ CMOS technology, the prototype chip measures less than $pm$4% variation in $K_{rm VCO} cdot I_{rm CP} / N$ (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.      

DDS技术在频率合成器中的应用

介绍了一般的频率合成技术—锁相环技术和直接数字合成技术（ＤＤＳ）与锁相环技术相结合的一种新的频率合成器。说明了这种新的合成器具有较高的频率稳定度、准确度和分辨力，以及具有体积小、功耗低、操作方便等特点，因而有广泛的应用价值。     

Methods to Accelerate Transient Processes in Frequency Synthesizers

Methods to accelerate transient processes in frequency spectrum synthesizers based on the pulse phase-locked loop are considered. Methods to accelerate the output voltage of the loop filter unit when using the equivalent capacitance multiplication of the capacitor methods based on the circuits with an additional current source in the charge pump current source (CPCS) unit are proposed. Diagrams of transient processes for the automatic control of the output frequency are presented. The diagrams confirm that using the proposed decisions for control by an additional current source of the CPCS unit makes it possible to approximate the transition process to the optimal value of the response speed.     

无线通讯系统频率合成器结构设计综述

在介绍无线通讯领域频率合成器主要设计指标的基础上,针对不同的设计指标,比较和分析了各种频率合成器的结构设计;详细地介绍了现在被广泛研究的小数型频率合成器和消除小数杂散的各种方法,其中,尤为详细地分析了采用ΣΔ调制技术的ΣΔ小数频率合成器;最后,对无线通讯领域频率合成器的应用前景和发展方向进行了展望。     

一种高性能低功耗直接数字频率合成器的设计

文章基于分段线性近似算法提出分段泰勒二阶近似算法，从频谱纯度分析了该算法的优越性，讨论了系数位数和分段数的选取，最后结合硬件优化的系统结构，设计实现了SFDR达102．3dB的数字频率合成器。综合结果表明，该算法实现的系统面积上要比分段线性近似算法的系统小20％，功耗上也小39．5％。与现有的其他数字频率合成器比较表明，在设计高频谱性能DDFS方面，其在功耗和面积上都具有较大优势。     

一种实现自调谐频率综合器的算法和结构

在集成的频率综合器中 ,工艺、温度和电源电压的变化使得频率综合器产生的中心频率和频率调谐范围与期望值发生偏移。文中指出了一种自调谐频率综合器的算法和结构 ,利用特殊结构的可编程压控振荡器和自调谐算法实现宽调谐范围的频率综合器 ,进而充分涵盖期望的输出频段。用 0 2 5 μmCMOS工艺设计了一个中心频率 2 2GHz,调谐范围为 338MHz的频率综合器 ,用于IEEE80 2 11b/g无线局域网系统的超外差收发机中 ,可以充分满足标准要求的 80MHz的调谐范围 ;给出了锁定某一目标频率时自调谐算法的具体工作过程 ,结果表明该算法和结构是正确的。