A Novel High CMRR High Input Impedance Differential Voltage-Mode KHN-Biquad Employing DO-DDCCs

In this work, a novel circuit configuration for realizing a differential voltage-mode Kerwin-Huelsman-Newcomb (KHN) biquad filter with high common-mode rejection ratio (CMRR) is presented. The proposed circuit is based on using the dual output differential difference current conveyor (DO-DDCC). The circuit uses three DO-DDCCs, two capacitors and five resistors. All the passive elements are grounded, which is important in integrated circuit implementation point of view. The differential voltage input signal is applied to high input impedance terminals, which is important in the voltage-mode operations. SPICE simulation results are included to verify the theory.     

Reliable CAD Analyses of CMOS Radio Frequency and Microwave Circuits Using Smoothed Gate Capacitance Models

The problems with convergence caused by both voltage- and charge-controlled models of MOSFET gate capacitances are often a limiting factor of the computer aided design tools. In the paper, an idea of the exponential smoothing of model discontinuities is proposed. The method is demonstrated on smoothing the gate capacitance discontinuity at zero drain-source voltage. An advanced integration algorithm convenient for the computer aided design of radio frequency and microwave CMOS circuits suppressing possible physically incorrect results of the traditional methods is also described. The updated model and algorithm are checked by analyzing a sophisticated CMOS flip-flop circuit.     

A New Low Distortion Analog Multiplier

A new method has been proposed to reduce the mobility degradation effect on square-law characteristic of the MOS transistor. This method has been applied to an analog multiplier to reduce the harmonic distortion. The analog multiplier designed operates with 5 V power supply. The linear operating range for each input is 3 V. In this operating range the circuit provides a total harmonic distortion of THD=0.6% from X input to the output and THD=0.5% from Y input to the output for operating as voltage controlled amplifier. Similarly, the 3 dB bandwidths are specified as 32 MHz and 34 MHz for X and Y inputs, respectively. The multiplier topology proposed allows external adjustment of the distortion, which can be considered as another important advantage of the circuit. The results show that the new method is effective for reducing distortion.     

Profiling Voids Embedded in a Slab by a Non-Linear Model

In this paper, by applying a non linear model for the electromagnetic inverse scattering, a technique for the dielectric profiling of a planarly layered medium is investigated and applied to void localization and diagnostics inside a homogeneous lossless slab (one-dimensional geometry). Data are collected under plane wave multifrequency normal incidence. Suitable finite dimensional representations for the unknown functions are introduced and their influence on the model is discussed. The resulting functional equation is solved by the method of weighted residuals and the solution algorithm amounts to minimizing a non quadratic function, where particular attention is devoted to reduce the occurrence of local minima. Finally, the inversion algorithm is validated by applications to both simulated and experimental data.     

Flexible Digital Receiver Architecture with Optimized Components

Future wireless communication systems require increased flexibility, lower power consumption, smaller size and decreasing costs for the terminals and therewith for the components. By replacing analogue by digital signal processing the degree of integration and the flexibility of a terminal with respect to multi-mode capability can be improved.In a highly integrated implementation the most critical components are the A/D-converter and the digital filter stages due to high speed and low power requirements. In this contribution a novel concept for a flexible, digital receiver with highly optimized components will be presented. The concept is based on down-conversion of the broadband receive signal to a low intermediate frequency. The main modules of the receiver are a properly designed ΔΣ-modulator for A/D-conversion, and novel digital filtering stages. It will be demonstrated, that the use of cascaded low-order wave digital lattice filters results in a number of advantages and makes a very efficient realization in VLSI-technology feasible.     

An Improved Small-Signal Parameter-Extraction Algorithm for GaN HEMT Devices

A highly efficient and accurate extraction algorithm for the small-signal equivalent-circuit parameters of a GaN high electron-mobility transistor device is presented. Elements of the extrinsic equivalent-circuit topology are evaluated using a modified “cold field-effect transistor” approach whereby the undesirable need to forward bias the device's gate terminal is avoided. Intrinsic elements are determined based on a circuit topology, which identifies, for the first time, a time delay in the output conductance of GaN-based devices. The validity of the proposed algorithm has been thoroughly verified with excellent correlation between the measured and modeled $S$-parameters up to 50 GHz.      

Modeling based real frequency technique

Usually commercially available software tools are used, to design matching networks for wireless communication systems. But a properly selected matching network topology with good initial element values must be supplied to these tools. Therefore, in this paper a modeling-based real frequency technique (M-RFT) is presented, to generate matching networks with initial element values. In the proposed method, output impedance data of the matching network are obtained in terms of ABCD-parameters of the load model. Then, they are modeled which in turn yields the desired matching network with initial element values. It is not needed to select a circuit topology for the matching network, which is the natural consequence of the matching processes. Also, there is no need to select the desired transducer power gain level; the proposed technique naturally provides a gain curve fluctuating around a flat level. Eventually, the initial design is improved by optimizing the performance of the matched system employing the commercially available computer aided design (CAD) packages. An algorithm and example are given, to illustrate the utilization of the proposed technique.     

A Novel Three-State ARQ Scheme for Variable Error-Tate Channels

This paper presents a new type of automatic-repeat-request (ARQ) scheme, Three-State ARQ (TS-ARQ), for error control in data transmission over a noisy channel. The new scheme is based on the Go-Back-N (GBN) protocol and uses three different methods of GBN protocols: basic GBN, n-copy GBN and continuous-GBN. The new ARQ model is applicable for channels having the variable noise level going from low through medium until very high levels. As it is known, such wireless channels are to be found in terrestrial and space (satellite) communications. This model is to be used for the estimation of the noise state in the channel and one of the methods is used, depending of the noise level. When the noise level is low GBN-ARQ is used, in the case of the medium noise level the n-copy GBN is used, and if the noise level is high continuous-GBN will be applied. This paper presents the method of determining the parameters and transfer moments from one state to another. An original mathematical model is given, together with evaluation results. These results are compared with the known methods and the conclusion that the described method provides some better performances is drowned. The implementation of this new procedure is simple as described in the flow chart given in the paper.     

A generalized method for calculating the RMS values of switchingpower converters

In this paper an analytical method is presented which allows the exact calculation of the RMS value of the state space variables of a switching power converter, whose starting point is the unified state-space representation of the switched networks and the end result is a complete form of equations that include both the DC and RMS values. The method proposed in this paper bridges the gap which exists between the state-space technique and the small signal approximation that departs from the steady state. Ripple values are negligible, compared to the steady state values themselves. A new extended circuit model is proposed whose fixed topology contains all the elements of any DC-to-DC converter, regardless of its detailed configuration, and by which different converters can be characterized in the form of a table conveniently stored in a computer data bank to provide a useful tool for computer aided design and optimization. Finally, examples are given for buck, boost, and buck-boost regulator topologies     

Mixed-integrator-based bi-quad cell for designing a continuous time filter

A new mixed-integrator-based bi-quad cell is proposed. An alternative synthesis mechanism of complex poles is proposed compared with source-follower-based bi-quad cells which is designed applying the positive feedback technique. Using the negative feedback technique to combine different integrators, the proposed bi-quad cell synthesizes complex poles for designing a continuous time filter. It exhibits various advantages including compact topology, high gain, no parasitic pole, no CMFB circuit, and high capability. The fourth-order Butterworth lowpass filter using the proposed cells has been fabricated in 0.18 μm CMOS technology. The active area occupied by the filter with test buffer is only 200×170 μm2. The proposed filter consumes a low power of 201 μW and achieves a 68.5 dB dynamic range.     

一种MHz光耦隔离放大器的设计与分析

本文设计了一种基于高线性度高带宽模拟光耦HCNR201芯片的MHz光耦隔离放大器电路,主要应用于计算机数据采集系统中,对其信号进行隔离从而实现过电压保护和提高共模抑制比.HCNR201光耦器件具有双光电二极管结构,使电路在输入端构成反馈环节,消除了光耦的电流传输比对直流增益的影响,为了方便分析建立了它的等效电路.利用线性控制系统的理论方法建立了所设计的隔离放大器电路的数学模型,推导出了电路的传递函数,对电路进行了理论分析和参数优化,并给出了分析设计结果.同时研制了隔离电路并对其进行了实验测试,实验结果与理论分析结果比较一致,符合设计要求,其理论分析方法可以为类似电路设计提供参考.     

High efficiency microwave rectenna circuit: modelling and design

An equivalent circuit approach used for the modelling of a system consisting of an antenna and an RF/DC rectifying circuit (rectenna) is presented. It is shown that using this approach, no electromagnetic simulation tool is required for the simulation and optimisation of the overall circuit. The realised rectenna operates at 2.45 GHz, and shows very good agreement between the predicted efficiency using the presented model (about 75%) and the measured one.     

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer

This paper presents a new design of a grounded active inductor (AI) with an improved topology based on Manetakis regulated cascode active inductor comprising of three control voltages for tunability. An additional pMOST was introduced in the design as a drain load at the output of nMOST source follower. The aim of this work is to design a CMOS AI at Ku band using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. Firstly, a reasonable AI operating at Ku band was manually designed using a 130 nm technology. This circuit and its design variables were fed to AIDA-C as an element of the initial population. Then the sizing of the proposed AI MOSTs was optimized. AIDA-C circuit sizing tool is able to achieve not only one but a set of solutions for the AI exhibiting high quality factor at a predefined Ku band operating frequency. This set of alternative Pareto optimal solutions enables the designer to choose the most suitable circuit sizing for a given application. AI’s main performance parameters in terms of s parameters (s₁₁), quality factor (Q), inductance value (L), linearity, noise figure, power consumption and tunability based on control and biasing voltages are presented. Layout of the optimized AI is also presented. This AI was used to design active filters. Their selectivity, insertion losses and noise analysis is presented and discussed.     

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

A novel topology of phase detector (PD) for applications in clock recovery systems from nonreturn-to-zero data is presented in this paper. The PD operates directly on the data stream, without requiring preprocessing, and behaves like a sampling-type PD, providing a sinusoidal phase characteristic. The triple-tail cell principle is exploited to obtain a circuit topology suitable to low-voltage high-speed applications, with a very simple structure and thus limited jitter generation. A model is proposed to understand circuit behavior and optimize its design. The PD has been used in a clock-and-data recovery circuit for 10-Gb/s optical communications, and measurements in agreement with SONET specifications are reported.     

A wideband high-CMRR single-ended to differential converter

A novel circuit topology that provides wideband single-ended to differential conversion is presented. The proposed circuit exploits a negative feedback loop to generate a second input signal for a differential pair, thus obtaining 6 dB extra conversion gain and higher CMRR with respect to a simple differential pair driven single-ended. A signal and noise model for the circuit is proposed, based on admittance parameters and the use of a novel analysis technique to open the feedback loop while maintaining closed loop loading effects. The model is exploited to derive design guidelines in bipolar and MOS technologies. Measurements on a test chip in STMicroelectronics BiCMOS7 technology are reported to compare the performance of the proposed topology and of a simple differential pair used as single-ended to differential converter.     

A novel topology for grounded-to-floating resistor conversion in CMOS technology

A new circuit topology to convert grounded resistors to an equivalent floating resistor is presented and discussed. The value of the resulting floating resistor equals the sum of the two grounded resistors. The new topology can be used to convert either passive, active grounded resistors or active grounded conductances. The new topology is used in the design of a current controlled very high value floating resistor in the range of GΩ. This was achieved by utilising the output conductance of two matched transistors operating in the subthreshold region and biased using a 500 nA current. The practicality of the new topology is demonstrated through the design of a very low frequency bandpass filter for artificial insect vision and pacemaker applications. Simulations results using Level 49 model parameters in HSPICE show an introduced total harmonic distortion of less than 0.25% for a 1 V_pp input signal in a 3.3 V 0.25 μm CMOS technology. Statistical modelling of the new topology is also presented and discussed.     

Design of broadband single matching networks

In general commercially available software tools are preferred, to design broadband matching networks for wireless communication systems. But they need a properly selected matching network topology with good initial element values. Therefore, in this paper a new real frequency technique is presented, to generate broadband single matching networks with suitable initial element values. In the proposed method, load impedance is written in terms of ABCD-parameters of the desired matching network and the source resistor. Then, free parameters are optimized which in turn yields the desired matching network with initial element values. It is not needed to select a circuit topology for the matching network, which is the natural consequence of the matching processes. Also, there is no need to select the desired transducer power gain level; the proposed technique naturally provides a gain curve fluctuating around the final available level. Eventually, the initial design is improved by optimizing the performance of the matched system employing the commercially available computer-aided design (CAD) packages. An algorithm and two examples are given, to illustrate the utilization of the proposed technique.