Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

In this paper, we present a methodology for the simulation of continuous-time (CT) sigma-delta converters. This method, based on a fixed-step algorithm, permits not only a time-domain simulation of the modulator output but also the simulation of intermediary signals. The method is based on the discretization of the CT models and the use of a discrete simulator such as Simulink, which is more efficient than an analog simulator. By using filters with a sampling frequency that is higher than the modulator output frequency, the model can simulate input signals with a bandwidth that is higher than half the modulator sampling frequency. The transformation is exact in terms of noise transfer function and asymptotically exact in terms of signal transfer function (the transfer function from the modulator input to each stage filter output rapidly tends to the CT-model transfer function when the number of steps increases).     

Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation

A new Continuous-Time (CT) sigma-delta modulator (SDM) based on the well-known asynchronous SDM is proposed in this paper. To this end, the flash quantizer and the digital-to-analog converter (DAC) in a multibit (MB) CT-SDM clocked at a rate f_max are replaced by a single-bit (SB) comparator with hysteresis clocked at a higher rate f_s and a SB-DAC, respectively. By proper selection of the hysteresis in the comparator and the ratio F = f_s/f_max, the performances of both modulators are shown to be equivalent. The comparator with hysteresis and the loop filter produce, in the modulator output, a limit cycle of frequency /max which is modulated by the input signal. Therefore, the modulator output can be considered to be a pulsewidth (PW) modulated signal with a frequency approximately equal to /max, and the proposed modulator is called a PW-SDM. Despite the high sampling rate of the comparator output, the integrators and the SB-DAC of the proposed modulator have the same speed requirements as those of the equivalent conventional MB-SDM. On the other hand, in the proposed modulator there are not MB (analog-to-digital or digital-to-analog) converters. Therefore, for a given set of specifications, the proposed PW-SDM is expected to consume less power and area than its equivalent conventional MB modulator.     

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma–delta $(SigmaDelta)$ modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology—which is suited for implementation in low-power applications—analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.      

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time Sigma–Delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD.      

On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma–Delta Modulators

This paper deals with one of the most outstanding advantages of continuous-time (CT) sigma-delta modulators compared to their discrete-time counterparts: the implicit anti-aliasing feature (AAF). Although inherent in any CT architecture, analysis of anti-aliasing properties has mostly been restricted to single-stage modulators in the past. In this contribution, extensions on analysis methods for the study of the AAF of CT multistage noise-shaping architectures are covered. A theoretical model is introduced and confirmed through simulation results. Contrary to previous belief, the results indicate that usually all stages of a cascaded architecture are involved in the anti-aliasing behaviour and hence that it is not solely determined by the first stage.     

New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma–delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.      

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

Electromechanical-Filter-Based Bandpass Sigma–Delta Modulator

This brief proposes an electromechanical-filter-based continuous-time (CT) bandpass (BP) sigma-delta modulator for wideband digitization at high intermediate frequency (> 70 MHz). Both the mechanically coupled microelectromechanical system and the longitudinally coupled surface acoustic wave (SAW) filters can be employed as loop filters. The advantages of the electromechanical filter are its low power consumption and accurate center frequency without the need for tuning. As a proof of concept, a fourth-order BP sigma-delta modulator is demonstrated with a 110-MHz SAW filter. Realized in a 0.35- mum SiGe heterojunction-bipolar-transistor bipolar complimentary metal-oxide-semiconductor technology, the prototype chip is clocked at 440 MHz and achieves 65-dB DR and 60-dB SNDR over 1 MHz, as well as 58-dB DR and 53-dB SNDR over the 3.84-MHz signal band. The total power consumption is 57 mW under a 3-V supply.     

Resonators in Open-Loop Sigma–Delta Modulators

In this paper, we introduce the modulo resonator for use in analog-to-digital open-loop sigma-delta modulators (OLSDMs). The OLSDM presented in this paper is intended for use in high-accuracy (14-bit) high-speed analog-to-digital converters. The modulo resonator is used with a modulo notch filter to insert a zero in the noise transfer function at a nonzero frequency. The effect of finite gain in modulo integrators and resonators is described and verified through simulation. The modulo resonator and a previously published modulo integrator are used in a behavioral model of a switched-capacitor fifth-order OLSDM with more than 13-bit effective number of bits for an oversampling ratio of four. We prove for the N -order OLSDM that the number of bits in the quantizer (B) must be larger than N to ensure equivalence between open-loop sigma-delta modulation and sigma-delta modulation.     

A 12-bit, 1-MHz, two-step flash ADC

A monolithic 12-b 1 MHz, two-step flash analog-to-digital converter (ADC) has been implemented in standard 3-μm CMOS technology. A 12-b accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter offset, gain, and nonlinearity errors. The converter differential nonlinearity errors below 1/2 LSB and the S/(N+D) signal to noise is 70 dB for 100-kHz analog input     

A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC inSiGe

This paper demonstrates the design of an integrated fourth-order bandpass sigma-delta converter, which is capable of digitizing a 200-kHz band at 200 MHz with 11-bit accuracy. The converter has been successfully fabricated in a 50-GHz SiGe bipolar technology, and the modulator consumes 21 mA at 3 V. The converter is aimed at the digitization of wireless signals at a high first intermediate frequency with a wide dynamic range     

A 12-Bit, 10-MHz Bandwidth, Continuous-Time $SigmaDelta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 mum times 660 mum. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SigmaDelta ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-icm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages.The ADC is realized in the 0.13-tt,m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage.Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage,such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm2.     

Analytical Settling Noise Models of Single-Loop Sigma–Delta ADCs

Switched-capacitor integrators are the basic building components for sigma-delta (SigmaDelta) modulators, and their incomplete charge transfer (settling problem) constitutes one of the dominant error sources in SigmaDelta modulators. Due to the complexity of the settling problem, analytic models for related noises are nonexistent. In this brief, closed forms of settling error models are obtained and represented as functions of SigmaDelta modulator system parameters. Both behavioral simulations and transistor-level circuit simulations are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate.     

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a $V_{rm TH}$ generator using a replica of the original comparator is also proposed to compensate for $V_{rm TH}$ deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.      

Bit-Stream Adders and Multipliers for Tri-Level Sigma–Delta Modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.     

Adaptive Noise Cancellation Techniques in Sigma–Delta Analog-to-Digital Converters

Adaptive noise cancellation (ANC) techniques that extract a desired signal from background noise have many applications in different engineering disciplines. In ANC, the corrupted signal is passed through a filter that tends to suppress the noise while leaving the original signal unchanged. This paper demonstrates that the adaptive noise cancellation technique can be embedded in the digital signal postprocessing of a sigma-delta analog-to-digital converter and effectively reduces the quantization noise as well as the thermal noise at the output of the converter. The combination of ANC and the noise-shaping technique enable high-resolution analog-to-digital conversion in wideband applications where noise shaping alone cannot provide enough suppression of quantization noise due to the low oversampling ratio.