A high-performance end system architecture for real-time CORBA

Many application domains (e.g., avionics, telecommunications, and multimedia) require real-time guarantees from the underlying networks, operating systems, and middleware components to achieve their quality of service (QoS) requirements. In addition to providing end-to-end QoS guarantees, applications in these domains must be flexible and reusable. Requirements for flexibility and reusability motivate the use of object-oriented middleware like the Common Object Request Broker Architecture (CORBA). However, the performance of current CORBA implementations is not yet suited for hard real-time systems (e.g., avionics) and constrained latency systems (e.g., teleconferencing). This article describes the architectural features and optimizations required to develop real-time ORB end systems that can deliver end-to-end QoS guarantees to applications. While some operating systems, networks, and protocols now support real-time scheduling, they do not provide integrated solutions. The main thrust of this article is that advances in real-time distributed object computing can be achieved only by systematically pinpointing performance bottlenecks; optimizing the performance of networks, ORB end systems, common services, and applications; and simultaneously integrating techniques and tools that simplify application development     

An Overview of a Compiler for Mapping Software Binaries to Hardware

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (FPGAs) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C 6211 DSP (VLIW) and the ARM 922 T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix FPGAs. We record overall performance gains of 1.5-26.9 for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.     

Generating efficient protocol code from an abstract specification

A protocol compiler takes as input an abstract specification of a protocol and generates an implementation of that protocol. Protocol compilers usually produce inefficient code both in terms of code speed and code size. We show that the combination of two techniques makes it possible to build protocol compilers that generate efficient code. These techniques are: (i) the use of a compiler that generates from the specification a unique tree-shaped automation (rather than multiple independent automata) and (ii) the use of optimization techniques applied at the automation level, i.e., on the branches of the trees. We have developed a protocol compiler that uses both these techniques. The compiler takes as the input a protocol specification written in the synchronous language Esterel. The specification is compiled into a unique automation by the Esterel front end compiler. The automation is then optimized and converted into C code by our protocol optimizer called HIPPCO. HIPPCO improves the code performance and reduces the code size by simultaneously optimizing the performance of the common path and optimizing the size of the uncommon path. We evaluate the gain expected with our approach on a real-life example, namely a working subset of the TCP protocol generated from an Esterel specification. We compare the protocol code generated with our approach to that derived from the standard BSD TCP implementation. The results are very encouraging. HIPPCO-generated code executes up to 25% fewer instructions than the BSD code for input packet processing while only increasing the code size by 25%     

A novel multicast traffic engineering technique in SDN using TLBO algorithm

In recent years, multicast communication is widely used by network providers to deliver multimedia contents. Quality of service (QoS) provisioning is one of the most important issues while transmitting multimedia contents using multicast. Traditional IP multicasting techniques suffer from reliability, scalability and have limitations to provide appropriate QoS for multimedia applications based on service level agreement (SLA). Nowadays, the advent of software defined networking (SDN), enables network providers to manage their networks dynamically and guarantee QoS parameters for customers based on SLA. SDN provides capabilities to monitor network resources and allows to dynamically configure desired multicasting policies. In this paper, we proposed a novel multicasting technique to guarantee QoS for multimedia applications over SDN. To deliver multimedia contents in an efficient manner, our proposed method models multicast routing as a delay constraint least cost (DCLC) problem. As DCLC problem is NP-Complete, we proposed an approximation algorithm using teaching–learning-based optimization to solve this problem. We evaluated our proposed method under different topologies. Experimental results confirmed that our proposed method outperforms IP multicast routing protocol, and it achieves a gain of about 25% for peak signal-to-noise ratio.     

Optimized dynamic compilation of dataflow representations for multimedia applications

This paper proposes two optimization methods based on dataflow representations and dynamic compilation that enhance flexibility and performance of multimedia applications. These optimization methods are intended to be used in an adaptive decoding context, or, in other terms, where decoders have the ability to adapt their decoding processes according to a bitstream. This adaptation is made possible by coupling the decoding information to process a stream inside a coded stream. In this paper, we use dataflow representations from the upcoming MPEG Reconfigurable Media Coding (RMC) standard to supply the decoding information to adaptive decoders. The benefits claimed by MPEG RMC are a reuse of coding tools between different specifications of decoder and an execution scalability on different processing units with a single specification, which can target either hardware and/or software platforms. These benefits are not yet achievable in practice as these specifications are not used at the receiver side in MPEG RMC. We valid these benefits and propose two optimizations for the generation and the execution of dataflow models: the first optimization takes benefits of the reuse of coding tools to reduce the time to obtain—configure—enforceable decoders. The second provides an efficient, dynamic, and scalable execution according to the features of the execution platform. We show the practical impact of these two optimizations on two decoder representations compliant with the MPEG-4 part 2 Simple Profile standard and the MPEG-4 Advanced Video Coding standard. The results shows that configuration time can be reduced by 3 and the performance of decoders can be increased by 50 %.     

An energy efficient middleware for an ad-hoc AAL wireless sensor network

DIA (Dispositivo Inteligente de Alarma, in Spanish) is an AAL (Ambient Assisted Living) system that allows to infer a potential dangerous action of an elderly person living alone at home. This inference is obtained by a specific sensorisation with sensor nodes (portables and fixes) and a reasoning layer embedded in a PC that learns of the users behaviour patterns and advices when actual one differs significantly of the normal patterns. In AAL systems, energy is a limited resource therefore sensor devices need to be properly managed to conserve energy. In this paper, we introduce the design and implementation of innovative and specific mechanisms at the sensory layer middleware which is capable of, first to discriminate spurious motion detections assuming that these signals do not resemble the patterns of real motion detections and, second to reduce the dynamics of messages by a sensor signal processing in order to compress the whole information in one single event. The middleware achieves power saving by modifying the raw information from sensors and adapting it to the predefined semantic of the reasoning layer. It manages the important task of data processing from sensors (raw information), and transfers the pre-processed information into the top layer of reasoning in a more energy efficient way. We also address the trade-off between reducing power consumption and reducing delay for incoming data. We present results from experiments using our implementation of these mechanisms at the middleware that comprises from node firmware to the PC driver. The number of messages of the proposed method with respect to the raw data is reduced by approximately 98.5%. The resources used in the PIR signal processing is reduced by approximately 85%. The resulting delay introduced is small (10–19 s) but system dynamics is slow enough to avoid contextualisation errors or reduction of system performance. We consider these results as very satisfactory.     

Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions

The video compression algorithms based on the 3D wavelet transform obtain excellent compression rates at the expense of huge memory requirements, that drastically affects the execution time of such applications. Its objective is to allow the real-time video compression based on the 3D fast wavelet transform. We show the hardware and software interaction for this multimedia application on a general-purpose processor. First, we mitigate the memory problem by exploiting the memory hierarchy of the processor using several techniques. As for instance, we implement and evaluate the blocking technique. We present two blocking approaches in particular: cube and rectangular, both of which differ in the way the original working set is divided. We also put forward the reuse of previous computations in order to decrease the number of memory accesses and floating point operations. Afterwards, we present several optimizations that cannot be applied by the compiler due to the characteristics of the algorithm. On the one hand, the Streaming SIMD Extensions (SSE) are used for some of the dimensions of the sequence (y and time), to reduce the number of floating point instructions, exploiting Data Level Parallelism. Then, we apply loop unrolling and data prefetching to specific parts of the code. On the other hand, the algorithm is vectorized by columns, allowing the use of SIMD instructions for the y dimension. Results show speedups of 5x in the execution time over a version compiled with the maximum optimizations of the Intel C/C++ compiler, maintaining the compression ratio and the video quality (PSNR) of the original encoder based on the 3D wavelet transform. Our experiments also show that, allowing the compiler to perform some of these optimizations (i.e. automatic code vectorization), causes performance slowdown, demonstrating the effectiveness of our optimizations.Special Issue on Media and Communication Applications on General Purpose Processors: Hardware and Software Issues/Journal of VLSI Signal Processing Systems/Dr. Eric Debes, (Lead) Guest Editor. Contact Author: Gregorio Bernabé.Gregorio Bernabé was born in Antibes (Alpes Maritimos, France) on 21 November 1974. He received the M.S. in Computer Science from the University of Murcia (Spain) in 1997. In 1998, he joined the Computer Engineering Department of the University of Murcia, where he is an Assistant Professor as well as a Ph. D. candidate. His current research interests include video compression using the Wavelet Transform, and the development of optimizations to improve the performance of the video compression algorithms based on the 3D wavelet transform.Jose M. Garcia was born in Valencia, Spain on 9 January, 1962. He received the MS and the PhD degrees in electrical engineering from the Technical University of Valencia (Valencia, Spain), in 1987 and 1991, respectively. In 1987 he joined the Computer Science Department at the University of Castilla-La Mancha at the Campus of Albacete (Spain). From 1987 to 1993, he was an Assistant Professor of Computer Architecture. In 1994 he became an Associate Professor at the University of Murcia (Spain). From 1995 to 1997 he served as Vice-Dean of the School of Computer Science. At present, he is the Director of the Computer Engineering Department, and also the Head of the Research Group on Parallel Computing and Architecture. He has developed several courses on Computer Structure, Peripheral Devices, Computer Architecture and Multicomputer Design. His current research interests include Multiprocessors Systems, Interconnection Networks, File Systems, Grid Computing and its Application in Multimedia Systems. He has published over 45 refereed papers in different Journals and Conferences in these fields. Dr. Garcia is a member of several international associations as IEEE Computer Society, ACM, USENIX, and also a member of some European associations (Euromicro and ATI).Pepe Gonzalez received the M.S. and Ph.D. degrees from the Universitat Politecnica de Catalunya (UPC). In January 2000, he joined the Computer Engineering Department of the University of Murcia, Spain, and became an Associate Professor in June 2001. In March 2002, he joined the Intel Barcelona Research Center, where he is a Senior Researcher. Currently, Pepe is working in new paradigms for the IA-32 family, in particular, Thermal-and Power-Aware clustered microarchitectures. pepe.gonzalez@intel.com     

Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications

In multimedia applications, run-time memory management support has to allow real-time memory de/allocation, retrieving and processing of data. Thus, its implementation must be designed to combine high speed, low power, large data storage capacity and a high memory bandwidth. In this paper, we assess the performance of our new system-level exploration methodology to optimise the memory management of typical multimedia applications in an extensively used 3D reconstruction image system [1, 2]. This methodology is based on an analysis of the number of memory accesses, normalised memory footprint¹ and energy estimations for the system studied. This results in an improvement of normalised memory footprint up to 44.2% and the estimated energy dissipation up to 22.6% over conventional static memory implementations in an optimised version of the driver application. Finally, our final version is able to scale perfectly the memory consumed in the system for a wide range of input parameters whereas the statically optimised version is unable to do this.The original version of this paper first appeared in the Proceedings of Signal Processing Systems 2003.Marc Leeman has as professional research interests hardware/software co-design, code optimisation in general and optimisation of dynamic data types and dynamic memory management for low power embedded systems in particular. Personal interests include Open and Free software development, software configuration and GNU/Debian package maintenance. He received an engineering degree, a master in artificial intelligence and a Ph.D. in electrical engineering in 1997, 1998 and 2004 respectively, all at the K.U. Leuven. He is a member of the IEEE Computer Society. Currently, he works as an R&D Engineer for Barco Control-rooms Division (BCD) on hardware/software co-design for streaming video products.David Atienza received the M.Sc. degree in Computer Sciences from the Complutense University of Madrid (UCM), Spain in 2001. Since then he has joined the Department of Computer Architecture and Automation of Complutense University of Madrid as a sandwich Ph.D. student half-time at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. His research interests include optimisation of dynamic memory management on multimedia and wireless network applications for low power and high performance embedded systems, computer architecture and high-level design automation.Geert Deconinck is Associate Professor (hoofddocent) at the K.U. Leuven (Belgium) since 2003 and staff member of the research group ELECTA (Electrical Energy and Computing Architectures). His research interests include the design and assessment of software-based solutions to meet dependability, real-time, and cost constraints for embedded systems. In this field, he has authored and co-authored more than 120 publications in international journals and conference proceedings. He received his M.Sc. in Electrical Engineering and his Ph.D. in Applied Sciences from the K.U. Leuven, Belgium in 1991 and 1996 respectively. He was a visiting professor (bijzonder gastdocent) at the K.U. Leuven in 1999–2003. - Flanders (Belgium) in the period 1997–2003.Vincenzo De Florio received his MSc degree in computer science in 1987 and his PhD degree in engineering in 2000, respectively from the University of Bari, Italy, and the University of Leuven, Belgium. He is currently post-doctoral researcher at the University of Antwerp, where he is doing research on adaptive and dependable mobile applications. Previously he had been researcher and lecturer with Tecnopolis/SASIAM (ECMI School for Advanced Studies in Industrial and Applied Mathematics) and member of Tecnopolis/Robotic lab, where he was responsible for design of parallel robotic vision applications. Currently he is also a reviewer for several conferences and for the Journal of System Architectures.José M. Mendías received the M.Sc. and Ph.D. degrees in physics from the Complutense University of Madrid in 1992 and 1998, respectively. He joined the Department of Computer Architecture and Systems Engineering, Complutense University in 1992 as a lecturer, and became an associate professor in 2001. Since 2002, he is Vice-dean of the Computer Science Faculty at the same University. His current research interests include design automation, computer architecture and formal methods.Chantal Ykman-Couvreur is born in 1956. She received the mathematics degree from the Facultes Universitaires Notre-Dame de la Paix of Namur in 1979. She first worked at PHILIPS Research Laboratory of Belgium, from 1979 until 1991. Her main activities were concentrated on information theory and coding, cryptography and multi-level logic synthesis for VLSI circuits. Then, she joined IMEC, where she was responsible at IMEC for the dynamic memory management and the system-level design flow in the Matisse compiler for network protocol components (ATM, Internet Protocol, etc). Currently, she works on the task concurrency management design flow in the Matador project.Francky Catthoor received the engineering degree and a Ph.D. in electrical engineering from the Katholieke Universiteit Leuven, Belgium in 1982 and 1987 respectively. Since 1987, he has headed several research domains in the area of high-level and system synthesis techniques and architectural methodologies, all within the Design Technology for Integrated Information and Telecom Systems (DESICS—formerly VSDM) division at the Inter-university Micro-Electronics Centre (IMEC), Heverlee, Belgium. Currently he is an IMEC fellow. He is part-time full professor at the EE department of the K.U. Leuven.In 1986 he received the Young Scientist Award from the Marconi International Fellowship Council. He has been associate editor for several IEEE and ACM journals, like Transactions on VLSI Signal Processing, Transactions on Multi-media, and ACM TODAES. He was the program chair of several conferences including ISSS97 and SIPS01.Rudy Lauwereins is vice-president of IMEC, Belgiums Interuniversity Micro-Electronic Centre, which performs research and development, ahead of industrial needs by 3 to 10 years, in microelectronics, nano-technology, enabling design methods and technologies for ICT systems. He leads the DESICS division of 185 researchers, currently focused on the development of re-configurable architectures, design methods and tools for wireless and multimedia applications. He is also a part-time Professor at the Katholieke Universiteit Leuven, Belgium. He had obtained a Ph.D. in Electrical Engineering in 1989. Rudy Lauwereins served in numerous international program committees and organisational committees, and gave many invited and keynote speeches. He is vice-chair of the board of DSP Valley and member of the board of several spin-off companies. He is a senior member of the IEEE.     

FHCF: A Simple and Efficient Scheduling Scheme for IEEE 802.11e Wireless LAN

The IEEE 802.11e medium access control (MAC) layer protocol is an emerging standard to support quality of service (QoS) in 802.11 wireless networks. Some recent work shows that the 802.11e hybrid coordination function (HCF) can improve significantly the QoS support in 802.11 networks. A simple HCF referenced scheduler has been proposed in the 802.11e which takes into account the QoS requirements of flows and allocates time to stations on the basis of the mean sending rate. As we show in this paper, this HCF referenced scheduling algorithm is only efficient and works well for flows with strict constant bit rate (CBR) characteristics. However, a lot of real-time applications, such as videoconferencing, have some variations in their packet sizes, sending rates or even have variable bit rate (VBR) characteristics. In this paper we propose FHCF, a simple and efficient scheduling algorithm for 802.11e that aims to be fair for both CBR and VBR flows. FHCF uses queue length estimations to tune its time allocation to mobile stations. We present analytical model evaluations and a set of simulations results, and provide performance comparisons with the 802.11e HCF referenced scheduler. Our performance study indicates that FHCF provides good fairness while supporting bandwidth and delay requirements for a large range of network loads. Pierre Ansel received a multidisciplinary in-depth scientific training in different fields such as Pure and Applied Mathematics, Physics, Mechanics, Computer Science and Economics from the Ecole Polytechnique, Palaiseau, France. Then, he joined the Ecole Nationale Superieure des Telecommunications, Paris, France in 2005 where he went further into electronics, databases, computer network security and high speed networks. He received a multidisciplinary master of sciences degree and an additional master of sciences degree in telecommunications in 2005. He did a summer internship in 2003 in INRIA, Sophia Antipolis, France where he worked on the Quality of Service in 802.11 networks at Planete Group, France. Then in 2004, he joined France Telecom R&D, Issy-les-Moulineaux, France to work on Intranet Security issues. He designed a WiFi security supervision architecture based on WiFi Intrusion Detection Sensors. He is currently a French civil servant and belongs to the French Telecommunications Corps. Qiang Ni received the B.Eng., M.Sc. and Ph.D. degrees from Hua Zhong University of Science and Technology (HUST), Wuhan City, China in 1993, 1996 and 1999 respectively. He is currently a faculty member in the Electronic and Computer Engineering Division,School of Engineering and Design, Brunel University, West London, U.K. Between 2004 and 2005 he was a Senior Researcher at the Hamilton Institute, National University of Ireland, Maynooth. From 1999 to 2001, he was a post-doctoral research fellow in the multimedia and wireless communication laboratory, HUST, China. He visited and conducted research at the wireless and networking group of Microsoft Research Asia Lab during the year of 2000. From Sept. 2001 until may 2004, he was a research staff member at the Planète group of INRIA Sophia Antipolis France. Since 2002, he has been active as a voting member at the IEEE 802.11 wireless LAN standard working group. His current research interests include communication protocol design and performance analysis for wireless networks, cross-layer optimizations, vertical handover and mobility management in mobile wireless networks, and adaptive multimedia transmission over hybrid wired/wireless networks. He has authored /co-authored over 40 international journal/conference papers, book chapters, and standard drafts in this field. He is a member of IEEE. E-mail: Qiang.Ni@ieee.org Thierry Turletti received the M.S. (1990) and the Ph.D. (1995) degrees in computer science both from the University of Nice – Sophia Antipolis, France. He has done his PhD studies in the RODEO group at INRIA Sophia Antipolis. During the year 1995–96, he was a postdoctoral fellow in the Telemedia, Networks and Systems group at LCS, MIT. He is currently a research scientist at the Planete group at INRIA Sophia Antipolis. His research interests include multimedia applications, congestion control and wireless networking. Dr. Turletti currently serves on the Editorial Board of Wireless Communications and Mobile Computing.     

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

A methodological framework for performance estimation of multimedia signal processing applications on different implementation platforms is presented. The methodology derives a complexity profile which is characteristic for an application, but completely platform-independent. By correlating the complexity profile with platform-specific data, performance estimation results for different platforms are obtained. The methodology is based on a reference software implementation of the targeted application, but is, in constrast to instruction-level profiling-based approaches, fully independent of its optimization degree. The proposed methodology is demonstrated by example of an MPEG-4 Advanced Simple Profile (ASP) video decoder. Performance estimation results are presented for two different platforms, a specialized VLIW media processor and an embedded general-purpose RISC processor, showing a high accuracy of he methodology. The approach can be employed to assist in design decisions in the specification phase of new architectures, in the selection process of a suitable target platform for a multimedia application, or in the optimization stage of a software implementation on a specific platform.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he worked at the NEC Information Technology Research Laboratories, Kawasaki, Japan, on efficient implementation of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization approaches for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL Research Center, Stuttgart, Germany. Since 1987 he is Professor in the Department of Electrical and Computer Engineering at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002.His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Dr. Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

Design and Tool Flow of Multimedia MPSoC Platforms

This paper surveys components that are useful to build programmable, predictable, composable, and scalable multiprocessor-system-on-a-chip (MPSoC) multimedia platforms that can deliver high performance at high power-efficiency. A design-time tool flow is proposed to exploit all forms of parallelism on such platforms. As a first proof of concept, the flow is used to parallelize a relatively simple video standard on a platform consisting of off-the-shelf components. As a second proof of concept, we present the design of a high-performance platform with state-of-the-art components. This platform targets real-time H.264 high-definition video encoding at an estimated power consumption of 700 mW.

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications. Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing. John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents. Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents. Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones. Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems. Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).     

End-to-end QoS framework for heterogeneous wired-cum-wireless networks

With information access becoming more and more ubiquitous, there is a need for providing QoS support for communication that spans wired and wireless networks. For the wired side, RSVP/SBM has been widely accepted as a flow reservation scheme in IEEE 802 style LANs. Thus, it would be desirable to investigate the integration of RSVP and a flow reservation scheme in wireless LANs, as an end-to-end solution for QoS guarantee in wired-cum-wireless networks. For this purpose, we propose WRESV, a lightweight RSVP-like flow reservation and admission control scheme for IEEE 802.11 wireless LANs. Using WRESV, wired/wireless integration can be easily implemented by cross-layer interaction at the Access Point. Main components of the integration are RSVP-WRESV parameter mapping and the initiation of new reservation messages, depending on where senders/receivers are located. In addition, to support smooth roaming of mobile users among different basic service sets (BSS), we devise an efficient handoff scheme that considers both the flow rate demand and network resource availability for continuous QoS support. Furthermore, various optimizations for supporting multicast session and QoS re-negotiation are proposed for better performance improvement. Extensive simulation results show that the proposed scheme is promising in enriching the QoS support of multimedia applications in heterogeneous wired-cum-wireless networks. Ming Li received his B.S. and M.S. in Engineering from Shanghai Jiao Tong University, China, in 1995 and 1998, respectively. He is currently a Ph.D. candidate in department of Computer Science, University of Texas at Dallas, where he received M.S. degree in Computer Science in Dec. 2001. His research interest includes QoSschemes for mobile ad-hoc networks and multimedia over wireless networks. Hua Zhu received the Ph.D. degree in Electrical Engineering from the University of Texas at Dallas, Texas. Since 2005, he has been working for San Diego Research Center, Inc., San Diego, CA, as a Research Engineer. His research interests include all layers of wireless communication systems. His particular interest is in L2/3 air interface design, performance analysis, and optimization for ad hoc and sensor networks. Imrich Chlamtac is the President of CREATE-NET and the Bruno Kessler Professor at the University of Trento, Italy. He has held various honorary and chaired professorships in USA and Europe including the Distinguished Chair in Telecommunications Professorship at the University of Texas at Dallas, Sackler Professroship at Tel Aviv University and has been on faculty at Technion, and UMass. Dr. Imrich Chlamtac has made significant contribution to various networking technologies as scientist, educator and entrepreneur. Dr. Chlamtac is the recipient of multiple awards and recognitions including Fellow of the IEEE, Fellow of the ACM, Fulbright Scholar, the ACM Award for Outstanding Contributions to Research on Mobility and the IEEE Award for Outstanding Technical Contributions to Wireless Personal Communications. Dr. Chlamtac published over three hundred and fifty refereed journal, book, and conference articles and is the co-author of four books. Dr. Chlamtac has widely contributed to the scientific community as founder and Chair of ACM Sigmobile, founder and steering committee chair of some of the lead conferences in networking including Mobicom, OptiComm, Mobiquitous, Broadnets, Securecomm. Dr. Chlamtac also serves as the founding Editor in Chief of the ACM/URSI/Springer Wireless Networks (WINET), the ACM/Springer Journal on Special Topics in Mobile Networks and Applications (MONET). B. Prahbakaran is with the faculty of Computer Science Department, University of Texas at Dallas. He has been working in the area of multimedia systems: animation & multimedia databases, authoring & presentation, resource management, and scalable web-based multimedia presentation servers. Dr. Prabhakaran received the prestigious National Science Foundation (NSF) CAREER Award in 2003 for his proposal on Animation Databases. He has published several research papers in various refereed conferences and journals in this area. He has served as guest-editor (special issue on Multimedia Authoring and Presentation) for ACM Multimedia Systems journal. He is also serving on the editorial board of Multimedia Tools and Applications journal, Kluwer Academic Publishers. He has also served as program committee member on several multimedia conferences and workshops. B. Prabhakaran has served as a visiting research faculty with the Department of Computer Science, University of Maryland, College Park. He also served as a faculty in the Department of Computer Science, National University of Singapore as well as in the Indian Institute of Technology, Madras, India.     

An Efficient Picture-Rate Up-Converter

The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.Aleksandar Berić received the Electrical Engineering Degree in 2001 from the University of Belgrade, Serbia. In 2002, he started his PhD at the University of Eindhoven, Netherlands. His fields of interest are algorithm/architecture co-design of video processing functions, motion estimation algorithms, low-power VLSI systems and processor architectures.Gerard de Haan received B.Sc., M.Sc., and Ph.D. degrees from Delft University of Technology in 1977, 1979 and 1992 respectively. He joined Philips Research in 1979. Currently he is a Research Fellow in the group Video Processing & Visual Perception of Philips Research Eindhoven and a Professor at the Eindhoven University of Technology. He has a particular interest in algorithms for motion estimation, scan rate conversion, and image enhancement. His work in these areas has resulted in several books, more than 100 scientific papers (www.ics.ele.tue.nl/∼dehaan/publications.html), more than 50 patents, and several commercially available ICs. He was the first place winner in the 1995 and 2002ICCE Outstanding Paper Awards program, the second place winner in 1997 and in 1998, and the 1998recipient of the Gilles Holst Award. In 2002, he received the Chester Sall Award from the IEEE Consumer Electronics Society. The Philips ‘Natural Motion Television’ concept, based on his PhD-study received the European Innovation Award of the Year 95/96 from the European Imaging and Sound Association, its successor ‘Digital Natural Motion’ received a Wall Street Journal Europe Business Innovation Award 2001. Gerard de Haan is a Senior Member of the IEEE.Ramanathan Sethuraman is senior scientist in the ESAS Group of Philips Research. He has a MSc in electrical engineering (‘92), and a PhD in electrical engineering (‘97) from the Indian Institute of Science for which he received the best MSc and PhD thesis awards at the Indian Institute of Science. His research interests include embedded system design, low-power VLSI systems, hardware-software co-design, VLSI systems for multimedia, VLSI signal processing and RISC/VLIW processor architectures. He has published more than 40 articles and has 20 patent filings. He has supervised 1 Ph.D student and 4 M.Sc students.Jef van Meerbergen received the Electrical Engineering Degree and the Ph. D. degree from the Katholieke Universiteit Leuven, Belgium, in 1975 and 1980, respectively. In 1979 he joined the Philips Research Laboratories in Eindhoven, the Netherlands where he started to design MOS digital circuits, domain-specific processors and general-purpose digital signal processors. He was the project leader of the Sigma-Pi project which delivered the first general purpose DSP within Philips.In 1985 he started working on application-driven high-level synthesis in the context of a European project in close cooperation with Imec. Initially this work was targeted towards DSP applications and resulted in the AR|T system which is used to design audio, video and communication functions.Later the application domain shifted towards high-throughput streaming applications for which the Phideo compiler was developed. This compiler was used for the design of feature box ICs for 100 Hz conversion for TV (Melzonic, Falconic) and for MPEG2 encoding (I.McIC). The Phideo paper received the best paper award at the 1997 ED&TC conference.His current interests are in design methods, heterogeneous multiprocessor systems, reconfigurable architectures and Networks-on-Silicon. Jef van Meerbergen is a Philips Research Fellow and Associate Editor of “Design Automation for Embedded Systems”. He is a part-time professor at the Eindhoven University of Technology.     

Enabling SIP-based sessions in ad hoc networks

The deployment of infrastructure-less ad hoc networks is suffering from the lack of applications in spite of active research over a decade. This problem can be solved to a certain extent by porting successful legacy Internet applications and protocols to the ad hoc network domain. Session Initiation Protocol (SIP) is designed to provide the signaling support for multimedia applications such as Internet telephony, Instant Messaging, Presence etc. SIP relies on the infrastructure of the Internet and an overlay of centralized SIP servers to enable the SIP endpoints discover each other and establish a session by exchanging SIP messages. However, such an infrastructure is unavailable in ad hoc networks. In this paper, we propose two approaches to solve this problem and enable SIP-based session setup in ad hoc networks (i) a loosely coupled approach, where the SIP endpoint discovery is decoupled from the routing procedure and (ii) a tightly coupled approach, which integrates the endpoint discovery with a fully distributed cluster based routing protocol that builds a virtual topology for efficient routing. Simulation experiments show that the tightly coupled approach performs better for (relatively) static multihop wireless networks than the loosely coupled approach in terms of the latency in SIP session setup. The loosely coupled approach, on the other hand, generally performs better in networks with random node mobility. The tightly coupled approach, however, has lower control overhead in both the cases. This work was partially done while the author was a graduate student in CReWMaN, University of Texas at Arlington. Dr. Nilanjan Banerjee is a Senior Research Engineer in the Networks Research group at Motorola India Research Labs. He is currently working on converged network systems. He received his Ph.D. and M.S. in computer science and engineering from University of Texas at Arlington. He received his B.E. degree in the same discipline from Jadavpur University, India. His research interests include telecom network architectures and protocols, identity management and network security, mobile and pervasive computing, measures for performance, modeling and simulation, and optimization in dynamic systems. Dr Arup Acharya is a Research Staff Member in the Internet Infrastructure and Computing Utilities group at IBM T.J. Watson Research Center and leads the Advanced Networking micropractice in On-Demand Innovation Services. His current work includes SIP-based services such as VoIP, Instant Messaging and Presence, and includes customer consulting engagements and providing subject matter expertise in corporate strategy teams. Presently, he is leading a IBM Research project on scalability and performance of SIP servers for large workloads. In addition, he also works on different topics in mobile/wireless networking such as mesh networks. He has published extensively in conferences/journals and has been awarded seven patents. Before joining IBM in 2000, he was with NEC C&C Research Laboratories, Princeton. He received a B.Tech degree in Computer Science from the Indian Institute of Technology, Kharagpur and a PhD in Computer Science from Rutgers University in 1995. Further information is available at Dr. Sajal K. Das is a Professor of Computer Science and Engineering and also the Founding Director of the Center for Research in Wireless Mobility and Networking (CReWMaN) at the University of Texas at Arlington (UTA). His current research interests include sensor networks, resource and mobility management in wireless networks, mobile and pervasive computing, wireless multimedia and QoS provisioning, wireless internet architectures and protocols, grid computing, applied graph theory and game theory. He has published over 400 research papers in these areas, holds four US patents in wireless internet and mobile networks. He received Best Paper Awards in IEEE PerCom’06, ACM MobiCom’99, ICOIN’02, ACM MSwiM’00 and ACM/IEEE PADS’97. He is also recipient of UTA’s Outstanding Faculty Research Award in Computer Science (2001 and 2003), College of Engineering Research Excellence Award (2003), the University Award for Distinguished record of Research (2005), and UTA Academy of Distinguished Scholars Award (2006). He serves as the Editor-in-Chief of Pervasive and Mobile Computing journal, and as Associate Editor of IEEE Transactions on Mobile Computing, ACM/Springer Wireless Networks, IEEE Transactions on Parallel and Distributed Systems. He has served as General or Program Chair and TPC member of numerous IEEE and ACM conferences. He is a member of IEEE TCCC and TCPP Executive Committees.     

Parallel Scalability of Video Decoders

An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are expected to contain. As a case study we investigate the parallelism available in video decoders, an important application domain now and in the future. Specifically, we analyze the parallel scalability of the H.264 decoding process. First we discuss the data structures and dependencies of H.264 and show what types of parallelism it allows to be exploited. We also show that previously proposed parallelization strategies such as slice-level, frame-level, and intra-frame macroblock (MB) level parallelism, are not sufficiently scalable. Based on the observation that inter-frame dependencies have a limited spatial range we propose a new parallelization strategy, called Dynamic 3D-Wave. It allows certain MBs of consecutive frames to be decoded in parallel. Using this new strategy we analyze the limits to the available MB-level parallelism in H.264. Using real movie sequences we find a maximum MB parallelism ranging from 4000 to 7000. We also perform a case study to assess the practical value and possibilities of a highly parallelized H.264 application. The results show that H.264 exhibits sufficient parallelism to efficiently exploit the capabilities of future manycore CMPs.

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.Sebastien Bilavarn received the M.S. degree from Rennes University (France) in 1998 and the PhD degree in Electrical Engineering from South Brittany University in 2002. Since June 2002, he works as a post-doc fellow at Signal Processing Institute, Swiss Federal Institute of Technology (EPFL). Sebastiens research interests include design methodologies for embedded systems, reconfigurable computing and Digital Signal Processing. Currently, his work focuses on using Adaptive Computing Systems to optimise computer architectures, which is a collaboration with the Architecture Research Lab of the System Technology Labs, Intel Corporation.Eric Debes received a M.S. in Electrical and Computer Engineering from Supélec, France in 1996, a M.S. in Electrical Engineering from the Technical University Darmstadt, Germany in 1997 and a PhD in Signal Processing from the Swiss Federal Institute of Technology. Since 2001 he has been a Researcher in the Architecture Research Lab of the System Technology Labs, Intel Corporation, Santa Clara, California. Erics research interests include image and video coding and processing algorithms as well as computer architecture and parallelism. At Intel he has been working together with different processor teams and microarchitecture research groups on the definition of new media and communication features (including new SIMD and streaming instructions, multicore processors and low-power architectures) in the CPU and the chipset to provide better media application performance and end user quality of service with a given system and processor power envelope and/or energy budget. More recently Eric has been working on system-on-chip modelling, processor and system power estimation and architecture design space exploration for consumer electronics applications. He is a member of the IEEE, of the ACM and of the SPIE.Pierre Vandergheynst received the M.S. degree in physics and the Ph.D. degree in mathematical physics from the Université catholique de Louvain, Belgium, in 1995 and 1998 respectively. From 1998 to 2001, he was a Postdoctoral Researcher with the Signal Processing Laboratory, Swiss Federal Institute of Technology (EPFL), in Lausanne, Switzerland. He is now an Assistant Professor of Visual Information Processing at EPFL, where is research focuses on computer vision, data processing and mathematical tools for visual information processing. Prof. Vandergheynst is Co-Editor-in-Chief of Signal Processing and member of the IEEE.Jean-Philippe Diguet received the M.S degree and the PhD degree from Rennes University (France) in 1993 and 1996 respectively. His thesis focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. From 1997 to 2002, he has been an associated professor at the South Brittany University and member of the LESTER laboratory. In 2003/04, he has initiated and created an innovating company in the domain of short range wireless communications. In 2004, he obtains a CNRS researcher position. His current work focuses on design space exploration of embedded systems, real-time scheduling in the context of hardware/software architecture configurations. Within the LESTER laboratory, he heads the “Design Trotter” team focusing on EDA methods and tools.