Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

嵌入式存储器的测试及可测性设计研究

引言近年来,消费者对电子产品的更高性能和更小尺寸的要求持续推动着SoC（系统级芯片）产品集成水平的提高,并促使其具有更多的功能和更好的性能。要继续推动这种无止境的需求以及继续解决器件集成领域的挑战,最关键的是要在深亚微米半导体的设计、工艺、封装和测试领域获得持续的进步。SoC是采用IP复用技术的一种标准设计结构,在多功能电子产品中得到了广泛的应用。     

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.     

从ARM体系看嵌入式处理器的发展

文章介绍了ARM体系的发展历史，它的指令集特点，程序模型和利用ARM体系处理器的软件开发和硬件调试过程。同时从ARM体系，我们也可以看到RISC在嵌入式处理器领域的优势所在，以及它们将来必然在SOC（系统芯片）中获得广泛应用。     

新型散射信道测试机的设计与实现

针对散射信道测试的必要性,设计了能够自动存储测试数据、达到无人值守状态的新型散射信道测试机。介绍了测试机的组成、工作原理和技术优势,详细剖析了基于Nios II的SD卡存储技术和载波频率校准技术的设计思路和实现方案,给出了新型散射信道测试机的性能测试结果。结果表明,新型散射信道测试机测试精度高、检测能力强,自动存储功能稳定可靠。     

粗糙集和支持向量机在复杂电路系统诊断中的应用

为了解决复杂电路系统故障样本少、特征信息冗杂的问题,提出了一种基于粗糙集属性约简理论和支持向量机分类方法相结合的故障诊断方法.首先采用粗糙集约简故障模式库中的冗余特征属性和矛盾样本,然后提取最简故障特征模式作为支持向量机的学习样本,通过样本训练使构建的支持向量机多分类器能够快速实现故障诊断的目的.最后,通过仿真算例验证了该方法在小样本故障识别上的有效性和可行性.     

Compilation Methods for the Address Calculation Units of Embedded Processor Systems

An essential component of today's embedded system is an instruction-set processor running real-time software. All variations of these core components contain at least the minimum data-flow processing capabilities, while a certain class contain specialized units for highly data-intensive operations for Digital Signal Processing (DSP). For the required level of memory interaction, the parallel executing Address Calculation Unit (ACU) is often used to tune the architecture to the memory access characteristics of the application. The design of the ACU is performance critical. In today's typical design flow, this design task is somewhat driven by intuition as the transformation from application algorithm to architecture is complex and the exploration space is immense. Automatic utilities to aid the designer are essential; however, the key compilation techniques which map high-level language constructs onto addressing units have lagged far behind the emergence of these units. This paper presents a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs. In addition to being an enhancement to existing compiler systems, the ArrSyn utility may be used as an aid to architecture exploration. A simple specification of the addressing resources and basic operations drives the available transformations and allows the designer to quickly evaluate the effects on speed and code size of his/her algorithm. Thus, the designer can tune the design of the ACU toward the application constraints. ArrSyn has been successfully used together with a C compiler developed for a VLIW architecture for an MPEG audio decoding application. The combination of these methods with the C compiler showed on average a 39% speedup and 29% code size reduction for a representative set of DSP benchmarks.     

A Simple Circuit to Reduce the Input Capacitance of Microelectrode Amplifiers

There are several specialized applications which require amplifiers with very low input capacitance. Two field effect transistors (FET's) can be cascaded in a source follower configuration to drive the drain of the input FET. The cascaded source follower provides at least an order of magnitude decrease in input capacitance. The cascaded source follower can be added to existing amplifiers or incorporated into new amplifier design with relatively little difficulty.     

实用的耐压仪200mA短路电流验证方法

实验室使用的耐压测试仪主要技术指标是功率和跳脱电流,然而按标准要求其短路电流也是一项重要参数.在实验室评审中,常常要求提供耐压仪短路电流能力是否满足200mA的验收记录.然而对实验室如何验证短路电流达到200mA不是件容易的事,不仅有技术难度,还有具有相当危险性,毕竟是4000V高压下验证.该文就我们的实际经验,分享一种实用的间接验证方法.     

多任务并发测试技术在提高测试效率降低测试成本中的应用

本文介绍了多任务并发测试技术的基本原理。采用此技术后,可大大提升测试效率,降低测试成本。     

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.     

一种RISC微处理器的快速乘除法运算设计与实现

定点尾数乘除法器是相应32位浮点运算的核心部件,针对工控应用,本文采用半定制方法完成了设计并且采用TSMC0.18微米工艺实现.乘法器采用基4Booth编码,通过对符号位、隐含位的处理减少了部分积的生成,并在Wallace树求和过程中,引入4∶2压缩器,加快了求和速度.除法器采用改进的SRT算法,引入商位猜测、部分余并行计算、商位修正值选择电路.乘除法器均采用了进位保留加法器提高运算速度.后端物理实现表明,乘除法器的频率分别可到227 MHz,305 MHz,整体设计具有简洁、快速、计算准确的特征.     

双里德-索罗门码信号处理器的交织、反交织理论及电路设计

利用微和硬件结合的方法,设计了新颖的里德－索罗门信号处理器交织,反交织电路。实验证明当磁迹丢失数据达４０％时,仍能利用插恢复数据。该电路具有可集,电路简捷及可进行实时交织,反交织运算等优点。     

嵌入式内存数据库的一种数据组织方式

针对嵌入式系统对数据管理的实际需求,提出了一种数据组织方式.该方式采用基于内存页的物理存储方法和基于Hash表与T-树索引的逻辑组织方法,适用于在嵌入式系统中构建基于内存的关系型数据库.     

Optimization of Information Rate Upper and Lower Bounds for Channels With Memory

We consider the problem of minimizing upper bounds and maximizing lower bounds on information rates of stationary and ergodic discrete-time channels with memory. The channels we consider can have a finite number of states, such as partial response channels, or they can have an infinite state space, such as time-varying fading channels.      

集成电路振动试验夹具的设计与测试方法综述

详细地介绍了集成电路振动试验夹具的设计和测试方法,包括母夹具的结构类型,夹具的总重量、大小、 材料和结构等夹具设计的原则,以及测试夹具性能的方法.     

集成电路极性测试“微整机”研究与应用

集成电路极性测试一般指选择电路一个特定管脚进行电性能量测,快速判断电路放置是否反向、错位等,实现原理和集成电路开短路测试原理一致。目前集成电路极性测试多数依赖于功能强大、应用成熟的集成电路自动测试机(Automatic Test Equipment,ATE)实现,但是测试性价比没有任何竞争力。基于集成电路极性测试原理,采用纯硬件制作一款集成电路极性测试"微整机",在极性测试上达到与ATE同样的测试能力,并能和机械手(Handler)进行信息交互,实现自动化测试,具备简单、稳定、高效和极低成本的特点。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。     

复杂互连结构传输性能分析及等效电路

信号完整性在某种程度上已经成为了限制当前高速电子系统设计与发展的瓶颈.建立了由过孔、焊点、印制线构成的高速电路板复杂互连结构单元模型,在1 ～ 10 GHz频率范围内针对模型进行信号传输性能的研究.用高频结构仿真器(HFSS)针对不连续区域内印制线不同长度、焊盘不同半径进行仿真分析,总结这些参数对信号传输性能的影响,提出了复杂互连结构的等效电路模型,并提取参数值进行对比验证.结果表明,随着印制线长度的增加、焊盘半径的增加,信号传输的回波损耗(RL)越来越强.用先进设计系统(ADS)软件对等效电路进行模拟,其回波损耗在1～6 GHz频率范围内与HFSS仿真结果相差不超过1 dB,在6～10 GHz频率范围内相差不超过2 dB.     

嵌入式系统中电源管理电路的设计与实现

针对大部分嵌入式系统的电池电源管理问题,设计了一种为嵌入式系统——尤其是应用在手持式和便携式设备的嵌入式系统进行电源管理的单元电路模块。该电源管理电路以MAX8903为核心,具有输入范围宽、体积紧凑、外围电路简单、工作效率较高等优点,可以在嵌入式系统中用来管理电池充电、电源选择、电源检测等,很好地满足了电源管理单元的功能需求。