Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

Low-power high-performance double-gate fully depleted SOI circuitdesign

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added back-channel leakage; and how the coupling between the front- and back-gates affects circuit reliability. Our analyses over different technology generations using the MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability in controlling leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for best leakage control. Moreover, threshold variation may cause reliability problems for thin back-gate oxide DGFD SOI circuits operated at low supply voltage     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface     

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.     

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs     

Deep submicrometer double-gate fully-depleted SOI PMOS devices: aconcise short-channel effect threshold voltage model using a quasi-2Dapproach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices     

A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.     

Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.     

Nanoscale FD/SOI CMOS: thick or thin BOX?

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.     

Physical background of substrate current characteristics andhot-carrier immunity in short-channel ultrathin-film MOSFET's/SIMOX

We show experimentally that, in contrast to past simulation results, I_SUB(max/)I_D decreases with decreasing silicon layer thickness. This is supported by two-dimensional numerical simulation results: the above phenomenon results from the nonlocal effect and the slightly gate-overlapped LDD structure. We also show that the velocity overshoot effect can suppress I_SUB(max/)I_D in short-channel MOSFET/SIMOX. It is demonstrated that 0.1-μm-gate ultrathin-film nMOSFET/SIMOX will have a 10-year lifetime at the supply voltage of 1.6 V, although an abnormal degradation is indicated in such an extremely short-channel SOI device     

Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs

This paper discusses the importance of controlling the lateral diffusion of impurities around the source and drain (S/D) junctions in sub-100-nm channel single-gate silicon-on-insulator (SOI) MOSFETs. Since any reduction in lateral diffusion length must consider the tradeoff between drivability and short-channel effect with regard to the threshold voltage, optimization of lateral diffusion length is essential in the device design stage. We note that the net performance improvement offered by device-scaling is quite limited, even if lateral diffusion length is optimized in some way. It seems obvious that high-/spl kappa/ materials are needed in order to improve net device performance in the sub-100-nm technology regime. In addition, with regard to the impact of the thermal budget on lateral diffusion control, new doping materials such as Sb and In, will be required in the near future. In the case of nMOSFET, however, advanced structures, such as an elevated layer, and advanced annealing process are needed to provide enhanced control of S/D diffusion regions.     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

Modes of operation and radiation sensitivity of ultrathin SOItransistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology     

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V_th) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the ΔV_th of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices     

Short-channel single-gate SOI MOSFET model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.