共查询到18条相似文献,搜索用时 62 毫秒
1.
纳米固态及真空电子器件 《电子器件》2008,31(6)
传统MOS器件的阈值电压模型被广泛地用于分析Trench MOSFET的阈值电压,这种模型对于长沟道和均匀分布衬底的MOS器件来说很合适.但是对于Trench MOSFET器件来说却显现出越来越多的问题,这是因为Trench MOSFET的沟道方向是垂直的,其杂质分布也是非均匀的.本文基于二维电荷共享模型,给出了Trench MOSFET的一种新的阈值电压解析模型,该模型反映了器件的阈值电压随不同结构和工艺参数变化的规律,模型的结果和器件仿真软件Sivaco TCAD的仿真结果吻合较好.该模型较好地解决了以往所用的Trench MOSFET阈值电压模型计算不准确的问题. 相似文献
2.
通过在柱坐标系下求解二维泊松方程,建立了短沟道无结柱状围栅金属氧化物半导体场效应管的电势模型,并推导了阈值电压、亚阈值区电流和亚阈值摆幅的解析模型。在此基础上,分析了沟道长度、沟道直径和栅氧化层厚度等参数对阈值电压、亚阈值区电流和亚阈值摆幅的影响。最后,利用Atlas软件对器件进行了模拟研究。结果表明,根据解析模型得到的计算值与模拟值一致,验证了模型的准确性。这些模型可为设计和应用新型的短沟道无结柱状围栅金属氧化物半导体场效应管提供理论基础。 相似文献
3.
在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移.扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好. 相似文献
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在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移.扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好. 相似文献
5.
An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE. 相似文献
6.
提出了一种非对称双栅应变硅HALO掺杂沟道金属氧化物半导体场效应管结构.该器件前栅和背栅由两种不同功函数的金属构成,沟道为应变硅HALO掺杂沟道,靠近源区为低掺杂区域,靠近漏区为高掺杂区域.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,分别求解了前背栅表面势、前背栅表面电场及前背栅阈值电压,建立了双栅器件的表面势、表面电场和阈值电压解析模型.详细讨论了物理参数对解析模型的影响.研究结果表明,该器件能够很好的抑制短沟道效应、热载流子效应和漏致势垒降低效应.模型解析结果与DESSIS仿真结果吻合较好,证明了该模型的正确性. 相似文献
7.
本文提出一个非均匀掺杂、短沟道MOSFET阈电压的准二维解析模型。用此模型对各种不同条件下的微米、亚微米MOSFET的阈电压进行了计算,其结果与二维数值分析程序得到的结果相符甚好。本模型可用于电路分析程序,工艺容错分析及器件的优化设计。 相似文献
8.
A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration. 相似文献
9.
The influences of the main structure and physical parameters of the dual-gate GeOl MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium (Ge) channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect (SCE) and drain-induced barrier lowering (DIBL) effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10-18 nm and (5-9)×1017 cm-3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8-1 nm and 15-30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved: on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV. 相似文献
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Using an exact solution of two-dimensional Poisson’s equation in cylindrical coordinates,a new analytical model comprising electrostatic potential,electric field,threshold voltage and subthreshold current for halodoped surrounding-gate MOSFETs is developed.It is found that a new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of the silicon channel is much larger than that of the oxide.It is also revealed that moderate halo doping concentration,thin gate oxide thickness and small silicon channel radius are needed to improve the threshold voltage characteristics.The derived analytical model agrees well with a three-dimensional numerical device simulator ISE. 相似文献
12.
A surface potential based non-charge-sheet core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented. It is based on the exact surface potential solution of Poisson's equation and Pao-Sah's dual integral without the charge-sheet approximation, allowing the SRG-MOSFET characteristics to be adequately described by a single set of the analytic drain current equation in terms of the surface potential evaluated at the source and drain ends. It is valid for all operation regions and traces the transition from the linear to saturation and from the sub-threshold to strong inversion region without fitting-parameters, and verified by the 3-D numerical simulation. 相似文献
13.
A surface potential based non-charge-sheet core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented. It is based on the exact surface potential solution of Poisson's equation and Pao-Sah's dual integral without the charge-sheet approximation, allowing the SRG-MOSFET characteristics to be adequately described by a single set of the analytic drain current equation in terms of the surface potential evaluated at the source and drain ends. It is valid for all operation regions and traces the transition from the linear to saturation and from the sub-threshold to strong inversion region without fiRing-parameters, and verified by the 3-D numerical simulation. 相似文献
14.
For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ... 相似文献
15.
本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型.并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究.该模型中考虑以下参数:金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分.结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL.同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率.此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高.数值模拟器ISE验证了该模型的正确性. 相似文献
16.
A continuous surface potential versus voltage equation is proposed and then its solution is further discussed for a long channel intrinsic surrounding-gate (SRG) MOSFET from the accumulation to strong inversion region. The original equation is derived from the exact solution of a simplified Poisson equation and then the empirical correction is performed from the mathematical condition required by the continuity of the solution, which results in a continuous surface potential versus voltage equation, allowing the surface potential and the related derivatives to be described by an analytic solution from the accumulation to strong inversion region and from linear to the saturation region accurately and continuously. From these results, the dependences of surface potential and centric potential characteristics on device geometry are analyzed and the results are also verified with the 3-D numerical simulation from the aspect of accuracy and continuity tests. 相似文献
17.
A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks
n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations. 相似文献
18.
For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. 相似文献