1.5-V high-performance SC filters in BiCMOS technology

The authors describe two low-voltage switched-capacitor (SC) filters: one can operate from a minimum supply of 1.5 V and the other from a minimum supply of 2 V (for typical parameter values). Both filters use a fully differential architecture and are fabricated in a standard BiCMOS technology. The lowest supply filter, operated from a 2-V supply, has an SNR (signal-to-noise ratio) of 92 dB and a THD (total harmonic distortion) of -70 dB for a 2.4-V_pp differential signal. Power consumption and area per pole are 60 μW and 0.18 mm², respectively, with a clock frequency of 447 kHz. The realized filters can be used as building blocks to implement more complex functions, like the active synthesis of a given impedance in line-fed telecom systems     

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-railoutput swing

A low-voltage switched capacitor (SC) filter operated from a single 1 V supply and realized in a standard 0.5-μm CMOS technology is presented. Proper operation is obtained using the switched-opamp technique without any clock voltage multiplier or low-threshold devices. This makes the circuit compatible with future deep submicrometer technology. As opposed to previous switched-opamp implementations, the filter uses a fully differential topology. This allows operation with a rail-rail output swing and reduction of the number of opamps required to build high order infinite impulse response (IIR) filters. On the other hand, a low-voltage common-mode feedback (CMFB) circuit is required. In addition, the circuit uses an opamp which is only partially turned off during the off phase. This enables an increase in the maximum sampling frequency. The filter implements a bandpass response (f_s/f _o=4, Q=7) and it has been characterized with a 1.8 MHz sampling frequency. Its power consumption is about 160 μW. The filter is still fully functional down to 0.9 V supply voltage     

Log-domain wave filters

A systematic method for designing log-domain wave filters is presented. Wave filters simulate topologically and functionally passive doubly terminated LC ladder prototype filters of low sensitivity. The design in the log-domain is based on a transposition of the signal flow graph (SFG) that corresponds to the wave equivalent of elementary two-port blocks in the linear domain, to the corresponding log-domain SFG. This is achieved by using an appropriate set of complementary operators, in order to preserve the linear operation of the whole circuit. Simulation results of a fifth-order low-pass and a fourth-order bandpass log-domain wave filter are given, using HSPICE. The proposed circuits are suitable for low-voltage operation and in high-frequency applications.     

An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter

A tuning scheme for continuous-time high-Q biquad filters is presented. An improvement over the existing implementation of the modified-LMS Q-tuning scheme is proposed and efficiently combined with the frequency tuning based on phase-locked loops. The proposed scheme takes much less area without compromising the accuracy achieved previously. The proposed unified Q- and f/sub 0/-tuning scheme does not require the Q-tuning loop to be slower than the f/sub 0/-tuning loop. The optimal case is to have equal speeds for both loops. Also, a low-voltage pseudo-differential operational transconductance amplifier with inherent common-mode feedforward is introduced. The structure is fully symmetric and suitable for high-frequency applications. An experimental test chip is fabricated in standard CMOS 0.5-/spl mu/m technology, with a bandpass filter of center frequency 100 MHz and Q of 20, along with the proposed tuning scheme. The measured Q-tuning error is around 1%. Expected and experimental results are in good agreement.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

多输出端电流模式全差分积分器实现带通滤波器的方法及仿真

该文提出了利用低电压多输出端电流模式全差分积分器(MCDI)设计实现连续时间电流模式滤波器的方法.分析并模拟了MCDI及所提出的滤波器的特性,应用3.3V,0.5m,CMOS工艺参数仿真得到的二阶带通滤波器功耗仅为0.6mW左右,且其中心频率可在很宽的范围内调控.此外,这种滤波器还具有结构简单、对称性好、失真小等优点,适于全集成.     

An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

CAD tools for the synthesis and layout of SC filters and networks

This paper describes two programs for the synthesis and layout generation of SC filters and networks. The first part of the paper describes a technology-independent synthesis and optimization program for SC filters. The program allows for the exact synthesis of cascaded SC biquad and SC ladder filters. Two performance measures related to sensitivity and noise are employed to estimate the performance of the synthesized circuits and to select optimum realizations. The same measures are used in a novel capacitance assignment procedure. The second part of the paper describes a flexible SC layout generator, which can be adapted to various design rules and floorplans by means of a technology file. Area efficient layout is generated by placing individual circuit elements rather than building blocks. Crosstalk between conductors is minimized by a router that distinguishes between different kinds of nodes.1. The scaling of the biquad circuit is dependent on the position of the biquad in the cascade.2. This may not seem to be overly important, since high-pass-type filters do not occur that often in practical applications. If one considers, however, that SCSYN is to be used as a general filter synthesis program, thenevery filter must be automatically realizable. In such an environment, a CAD program that can design all but one type of filter is either quite useless or very limited indeed.3. Note that an SC filter, in contrast to a digital filter, may contain delay-free loops.     

用于高频的新颖开关电容积分器

本文研究了用于开关电容(SC)滤波器的离散积分器,所推荐的积分器是由无耗离散积分器(LDI)和双线性离散积分器的最佳线性结合而成,因此,称之为组合离散积分器(CDI)。由于这个积分器使正常转折频率增加一倍,并使高频离散积分器误差减少到最低限度,所以它对高频应用是理想的。文中给出了组合离散积分器的几种SC实现,并且还给出了以组合离散积分器为基础,模拟一般一阶和二阶的模拟滤波器单元的SC电路。     

On the use of Nauta's transconductor in low-frequency CMOS gm-C bandpass filters

This paper discusses the use of a transconductor, first proposed by Nauta for high frequency applications, in low frequency CMOS g_m -C bandpass filters. The behavior of the transconductor is examined in detail, showing that the robust implementation of higher-order low-voltage filters is possible for center frequencies in the lower megahertz region. The experimental results are presented of the realization of two prototypes, a 0.6-μm CMOS 18th-order real bandpass filter and a 0.35-μm CMOS 7th-order complex (14th-order bandpass) filter, both with a center frequency of 3 MHz and a passband of 1 MHz. These filters comply with the specifications for the channel-select stage of the Bluetooth short-range radio receiver     

A compact low-power BiCMOS log-domain filter

A third-order Chebyshev filter based on the log-domain principle and integrated in a 1-μm BiCMOS process is presented. It has a nominal cutoff frequency of 320 kHz corresponding to a bias current of 1 μA, and can be frequency tuned over almost three decades up to about 10 MHz. It operates with a nominal supply voltage of 1.2 V, maintaining a dynamic range (DR) at 1% THD of 57 dB. For cutoff frequencies in the range of 10 kHz, the supply voltage can be reduced down to 0.9 V. The filter occupies an active area of 0.25 mm² and dissipates 23 μW, corresponding to a power consumption per pole and edge frequency of only 24 pJ. These results demonstrate the potential of log-domain filters for very low-voltage and low-power applications     

1.5 V tunable Square-Root Domain filter

A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 /spl mu/m CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

Low-voltage fully differential switched-current filters

An accurate high-frequency switched-current integrator based on low-voltage fully-differential folded-cascode current copiers is presented. A five-pole lowpass ladder filter has been integrated using a 1.2 μm n-well CMOS process without floating precision linear capacitors. Experimental results show an accurate filter response for sampling frequencies up to 5 MHz. Using a nominal 3.3 V power supply, the measured dynamic range is 66 dB and the power dissipation is 10 mW/pole     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

CMOS亚阈值特性的低频低压微功耗电路的设计与模拟

工作在亚阈值状态的MOS晶体管具有极小的工作电流和类似于双极型晶体管的指数特性,因此适合于实现微功耗的外部线性内部非线性电流型电路.为了适合于低电源电压的运用,本文给出了一种新型的电流型四象限乘法器以及滤波器,振荡器等基本单元电路,并利用标准0.6-μm CMOS的工艺参数以锁相环为例进行了性能模拟验证.     

Charge-domain integrated circuits for signal processing

A new class of integrated circuits called charge-domain device has been developed for performing enhanced monolithic signal processing. All signal-processing operations are accomplished by splitting, routing and combining charge packets, thus overcoming many of the limitations of alternative devices such as charge-coupled device (CCD) split-electrode transversal filters and switched capacitor filters. Charge manipulation techniques are described which allow poles as well as zeros of a transfer function to be implemented efficiently, leading to infinite impulse response monolithic filters suitable for high-frequency applications. Several test filters, including a narrowband 8-pole bandpass filter, are demonstrated. These charge-domain devices are useful in applications ranging from radio IF to radar to video signal processing with a high level of integration achievable on a single charge-domain integrated circuit.     

Biquad alternatives for high-frequency switched-capacitor filters

Biquad sections are the basic building block of practical switched-capacitor (SC) filters. The authors focus on the amenability of various biquad options for high-frequency operation. A comparison on the basis of analysis and a recent nonideal SC network simulation tool are confirmed by results from a VLSI 1.25-/spl mu/m CMOS test chip. A differencing-input SC biquad is shown to have a significant performance advantage over other circuits.