Rapid Anneal of Radiation-Induced Silicon-Sapphire Interface Charge Trapping

The rapid ahneal phenomenon of the radiation induced charge trapping at the silicon sapphire interface was experimentally investigated using a junction FET structure from 10 ?sec through 1 second after an ionizing radiation pulse for various fabrication parameters and bias conditions. The fabrication parameters investigated include type of starting sapphire (Czochralski, ribbon, and gradient furnace), sapphire polish, pre-epitaxial anneal environment (air and hydrogen), and epitaxial growth method (uniform and burst). The "back channel" rapid anneal effect was also characterized as a function of bias applied to the device during the radiation pulse as well as the bias applied during the anneal time. The results show that the rapid anneal time constant is essentially independent of the bias applied during the radiation pulse as well as during the anneal time, although the initial and final values of leakage current are functions of drain bias. The experimental results also show that the rapid anneal time constant is essentially independent of the type of starting sapphire, but is a function of the pre-epitaxial sapphire anneal environment and epitaxial growth method.     

Leakage Current Phenomena in Irradiated SOS Devices

A detailed study of ionizing radiation effects on SOS devices has been performed with emphasis placed on determining the mechanisms of back-channel leakage current phenomena. Behavior for n-channel transistors fabricated with both wet and dry gate oxides is compared and differences in radiation response are attributed to a larger density of hole traps in the sapphire for dry-oxide devices. It is observed that reduction of radiation-induced leakage current to very near its preirradiation value can be readily accomplished by continuing to irradiate a device under a condition of zero drain bias. Studies with low-energy electrons (6 - 45 keV) from a scanning electron microscope reveal that energy must be deposited in the sapphire in order to increase the leakage current and that energy deposition in the sapphire bulk is unimportant in terms of leakage current production. For the present devices, the region which is effective in producing such current extends into the sapphire a distance on the order of 2 ?m from the Si-Al2O3 interface. If hole traps are spatially distributed, then the dominant mechanism for reducing leakage current is shown to be injection of electrons from Si into Al2O3 where they neutralize trapped holes. A model for radiation-induced production and reduction of leakage current in SOS devices is described.     

Shubnikov-De Haas Oscillations Caused by a Two-Dimensional Leakage Channel on Silicon Mosfets Induced by Electron Irradiation

A possible failure mechanism of n-channel MOSFETs exposed to ionizing radiation are leakage currents between source and drain. This leakage begins to occur at relatively low radiation doses, and can seriously degrade the performance of an otherwise hardened CMOS device. In the present paper, we demonstrate by the observation of quantum oscillations in the magnetoresistance that by room temperature irradiation with high energy electrons an inversion layer is generated under the field oxide, which gives rise to leakage currents. Magnetoresistance oscillations may be observed, if in a degenerate electron gas the carrier mobility is sufficiently high to allow quantization of the electron movement in a magnetic field and the thermal energy is much smaller than the cyclotron energy. This oscillatory behaviour of the electrical resistance as a function of a magnetic field - the Shubnikov-de Haas effect - is a valuable tool to investigate the electronic parameters of bulk semiconductors and surface channels. Such experiments not only give firm evidence about the existence of a bypass inversion layer, but also yield information about the carrier density in the radiation induced channel. It turns out that the electrons behave like a two-dimensional free electron gas the density of which is independent of the gate voltage. Moreover, the experiments give knowledge about the influence of trapped charges, caused by the irradiation at the interface.     

不同设计参数MOS器件的射线总剂量效应

采用非加固工艺，通过设计加固手段实现具有辐射容忍性能的器件，可使器件抗辐射加固成本大为降低。本工作研究商用标准0.6μm体硅CMOS工艺下不同设计参数的MOS晶体管的γ射线总剂量辐照特性。通过对MOS器件在不同偏置情况下的总剂量辐照实验，分别对比了不同宽长比（W/L）NMOS管和PMOS管的总剂量辐照特性。研究表明，总剂量辐照引起阈值电压的漂移量对NMOS及PMOS管的W/L均不敏感；总剂量辐照引起亚阈区漏电流的增加随NMOS管W/L的减小而增加。研究结果可为抗辐射CMOS集成电路设计中晶体管参数的选择提供参考。     

Radiation Hardened CMOS/SOS

This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l?A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ?1V for the n-channel devices and ?2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.     

Effects of electron radiation on commercial power MOSFET with buck converter application

Microelectronic power converters such as buck and boost converter are required to be tolerant to radiations including electron radiation.This paper examines electron radiation effects on the Ⅰ-V characteristics of VDMOSFET and its corresponding effects in buck converter.Analysis of the electrical characteristics shows that after irradiation the threshold voltage and drain current for all VDMOSFETs degraded more than two orders of magnitude.The impact of this electrical degradation has been investigated in an application of typical buck converter circuit.The buck converter with n-channel switching transistor shows that after irradiation its output voltage increased with the drain current in the n-channel ZVN4424A VDMOSFET,while the buck converter with p-channel switching transistor shows its output voltage decreased with the drain current in the p-channel ZVP4424A VDMOSFET after irradiation.     

Effects of electron radiation on commercial power MOSFET with buck converter application

Microelectronic power converters such as buck and boost converter are required to be tolerant to radiations including electron radiation. This paper examines electron radiation effects on the Ⅰ-Ⅴ characteristics of VDMOSFET and its corresponding effects in buck converter. Analysis of the electrical characteristics shows that after irradiation the threshold voltage and drain current for all VDMOSFETs degraded more than two orders of magnitude. The impact of this electrical degradation has been investigated in an application of typical buck converter circuit. The buck converter with n-channel switching transistor shows that after irradiation its output voltage increased with the drain current in the n-channel ZVN4424 A VDMOSFET, while the buck converter with p-channel switching transistor shows its output voltage decreased with the drain current in the p-channel ZVP4424 A VDMOSFET after irradiation.     

Total ionizing dose effects in high voltage devices for flash memory

The effect of size and substrate bias conditions after irradiation on the total ionizing dose response of high voltage devices for flash memory has been investigated. Different sensitivity of transistors with different gate width was observed, which is well known as the radiation induced narrow channel effect. A charge sharing model was used to explain this effect. The negative substrate bias voltage after irradiation showed considerable impact on the parasitic transistor’s response by suppressing leakage current.     

Thin Film Silicon on Silicon Nitride for Radiation Hardened Dielectrically Isolated Misfet's

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric has been determined for a total ionizing dose up to 107 rads (Si). Junction FET's, whose active channel region is directly adjacent to the siliconsilicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si3N4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si3N4 are compared to results on similar devices with SiO2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed.     

EE80C196KC20单片机γ辐射总剂量效应

建立商用16位单片机EE80C196KC20辐射效应在线测试系统,利用60Co源在20rad（Si）/s的剂量率条件下研究了电离辐射的失效模式和敏感参数。实验获得了单片机的失效阈值,得到了功耗电流、I/O输出、PWM输出随总剂量的变化规律,从工艺和电路结构分析了敏感参数变化的物理机理,对抗辐射加固设计有重要意义。     

Dose-Rate Effects in the Permanent Threshold Voltage Shifts of MOS Transistors

Data has been collected that shows the permanent threshold voltage shift occurring in MOS transistors exposed to the same total dose of gamma radiation can be greater in a high dose-rate environment than in a low dose-rate environment. This dose-rate effect is ascribed to a "Photovoltaic" bias generation in the substrate of a device which results in an effective gate bias change (positive for P-channel and negative for N-channel transistors). The bias change ranges from 0 to ±1 volt during the radiation burst. Thus, in a high dose-rate ionizing environment, the permanent gate threshold voltage shift of an MOS device, which is known to be a function of the gate bias during irradiation, will exhibit an indirect dose-rate dependence which is caused by an internal change in instantaneous gate bias.     

瞬态闭锁试验在0.13 μm大规模集成电路中引起的潜在损伤

瞬态剂量率辐射试验会引起集成电路发生损伤或失效,其原因至少有两种：闭锁大电流引起的电路内部金属互连熔融;累积电离总剂量引起的氧化层电荷造成阈值电压偏移。本文以一种0.13 μm体硅CMOS处理器为对象,研究了瞬态剂量率和稳态电离总剂量辐射效应规律。结果表明：瞬态剂量率闭锁效应对处理器造成了显著的潜在损伤,导致其总剂量失效阈值从1 030 Gy(Si)降低至600 Gy(Si)。研究结论对于大规模集成电路的可靠性评估和指导辐射加固设计有重要参考意义。     

SiC器件单粒子效应敏感性分析

新一代航天器需要使用耐高压、功率损耗低的第3代半导体SiC器件,为了给器件选用和抗辐射设计提供依据,以SiC MOSFET和SiC二极管为对象,进行单粒子效应敏感性分析。重离子试验发现,在较低电压下,重离子会在SiC器件内部产生永久损伤,引起漏电流增加,甚至单粒子烧毁。SiC MOSFET和SiC二极管试验结果类似。试验结果表明SiC器件抗单粒子能力弱,与器件类型关系不大,与SiC材料有关。为了满足空间应用需求,有必要进一步开展SiC器件辐射效应机理、试验方法和器件加固技术等研究。     

4000系列CMOS器件的电离辐射感生漏电流

研究分析了４０００系列ＣＭＯＳ器件电离辐射感生漏电流的产生机制、变化特性及其与加固水平的关系，探讨了辐射感生静态功耗电流，其中特别是场氧化层漏电流的加固抑制方法。     

Optimization of the Neutron Radiation Tolerance of Junction Field Effect Transistors

The fast neutron irradiation induced degradation of junction field effect transistors has been studied in detail. A comparison of p-channel to n-channel devices has confirmed reported differences in hole and electron removal rates. The predicted increase of hardness with increasing channel dopant concentration is experimentally demonstrated, although channel dopant grading makes very heavily doped units difficult to attain in practice. Also, a device modification which allows attainment of breakdown voltages higher than those characteristic of the channel doping level is presented and experimentally verified. This modification made possible the construction of devices with breakdown voltages greater than fifty volts, which degraded by only 25% in transconductance at fluences of approximately l-3×1015 neutrons/cm2 (E > 10 kev, Triga). Thus, the technique offers promise in the construction of very radiation resistant devices with wide operating voltage ranges.     

Predicted Effects of Neutron Irradiation on GaAs Junction Field Effect Transistors

The fast-neutron-induced degradation of the properties of n-channel GaAs junction field effect transistors (JFET) is estimated and the results are compared with the effects produced in n-and p-channel silicon field effect transistors. The estimated degradation of the maximum transconductance, maximum drain current, pinch-off voltage, and cutoff frequency is based on electrical measurement data taken for fast-neutron-irradiated bulk n-type GaAs samples. It is concluded that n-channel GaAs JFET's should be at least as resistant to fast neutrons as either n-or p-channel Si JFET's.     

An Analysis of Ionizing Radiation Effects in Four-Layer Semiconductor Devices

The switching of a four-layer semiconductor device in an ionizing radiation environment is calculated by solving the charge transport equations to determine the motion of the electron and hole distributions and the changes in the electric field distribution throughout a one-dimensional device as a function of time. A discussion of the characteristic device turn-on as a function of the ionizing radiation exposure and external circuit and device parameters is presented. In addition to showing the detailed calculated device behavior, the theoretical and experimental results are compared.     

Investigation of Radiation Effects and Hardening Procedures for CMOS/SOS

Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO2 gate insulators. A modified gate oxidation process using steam and HCl has resulted in improved gate oxide hardness -- with threshold voltage shifts of less than two volts up to a total dose of 106 rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate process ing techniques. Post-irradiation values of less than 0.5?A/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 1011 cm-2 to 1012 cm-2 - peaking at a total dose of about 105 rads (Si). This effective charge decreases for increasing doses above 5×105 rads(Si). The decrease is attributed to radiation-induced interface states.     

0.18 μm MOS差分对管总剂量失配效应研究

为明确深亚微米MOS差分对管在电离辐射环境下晶体管失配表征方法及损伤机理,本文针对0.18 μm NMOS、PMOS差分对管,进行了⁶⁰Co γ总剂量辐射效应研究。研究结果表明：与PMOS差分对管相比,NMOS差分对管对总剂量辐照更敏感,主要表现在：1) 辐照引起NMOS差分对管转移特征曲线失配增加;2) NMOS差分对管阈值电压失配随辐照总剂量的增加而增大;3) 栅极电流辐照后稍有增加,失配随栅极电压的增加而增大。而PMOS差分对管在整个辐照过程中,无论是曲线还是参数均未出现明显变化,且失配亦未随辐照总剂量的增加而增大。     

星用典型CMOS器件54HC0460Co源辐射效应研究

给出了加固和非加固 5 4HC0 4电路在不同辐射偏置下的低剂量率辐射实验结果 ,探讨了电流转移曲线、辐射感生漏电流、阈值电压、转换电压随辐射剂量的变化关系。