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研究万兆以太网中的64B/66B的编解码规则及其内在的特性,提出了一种基于查找表和逻辑运算相结合的64B/66B编解码实现方法,具有使用资源少、编解码速度快、可靠性强等特点.该方法使用硬件描述语言Verilog HDL来实现64B/66B编解码的描述,通过Xilinx的FPGA器件进行仿真和综合,实现了具体的硬件电路,并且下载验证了该设计方法的有效性和可行性.不同速率的高速64B/66B编解码模块或芯片的设计可以采用该方法来实现. 相似文献
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指数哥伦布编码是H.264/AVC标准和AVS标准中熵编码的重要组成部分,其硬件实现好坏直接决定了编码器熵编码的性能。文中根据哥伦布编码和解码的特点,设计了一种高速的哥伦布编解码器。首先,用查找表的方式代替了首1检测等复杂操作,通过查找直接得出要编解码码字的长度;直接取出特定的要操作的数据,同时进行相应的操作,代替了传统的先移位,再进行相应操作的方式,使得指数哥伦布编解码器的关键路径变短,速度变快。其次,对哥伦布编解码器采用了多级流水的方式,进一步提升了主频。最后,在virtex5平台上进行测试,该编解码器的吞吐率均可达到400MPixel/s。这将远胜于当今图像解码专用芯片的编解码速度,也为图像高速压缩提供了硬件实现基础。 相似文献
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为提高8B/10B编解码的工作速度和简化逻辑方法,提出一种基于FPGA的8B/10B编解码系统设计方案.与现有的8B/10B编解码方案相比,该方案是一种利用FPGA实现8B/10B编解码的模块方法,接收模块在收到外部发送的并行数据时,通过直接查找映射的方法转换成利于传输的串行信号.串行信号经串并行转换模块,将数据经10B/8B解码模块解码还原成原始数据.为了更好实现数据的传输,系统加入了极性偏差RD控制.结果表明,该8B/10B编解码系统设计方案传输数据稳定,满足设计要求. 相似文献
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《电子科技文摘》2006,(10)
0626026产生非标准时钟频率的编程基准振荡器〔刊,中〕/William Grill//电子设计技术.—2006,(7).—118(C)0626027基于查找表和CORDIC算法的数控振荡器的设计〔刊,中〕/崔文//电子科技.—2006,(7).—23-25(D)研究了一种基于查找表和CORDIC(CoordinateRotation Digital Computer)算法相结合的数控振荡器(NCO)的实现方法,与仅基于查找表的方法相比,该方法结构简单、精度高、耗费资源少。仿真和验证结果表明,该设计是可行的,并易于FPGA实现。参40626028深亚微米工艺CMOS Gilbert混频器噪声分析〔刊,中〕/唐守龙//应用科学学报.—2… 相似文献
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HJ-1B卫星自发射以红外通道共进行了7次星上黑体定标,针对星上定标系数的验证工作开展较少,以MODIS第31、32通道为参考源,分别基于光谱响应差异和线性统计关系两种方法对HJ-1B红外通道星上定标系数进行验证.首先,计算两个传感器表观辐亮度的匹配关系,进而计算出HJ-1B红外通道的等效离表亮温,通过与HJ-1B红外通道基于星上定标系数反演得到的离表亮温进行比较,实现对星上定标系数的验证.通过半高宽法、矩方法和查找表法这三种不同的方法计算得到了2009年9月14日星上定标系数.结果表明:三种方法中,查找表法精度较高, 且HJ-1B查找表法星上定标系数反演亮温与基于光谱响应差异和线性统计关系计算的等效亮温偏差较小,分别为0.02 K和0.81 K.这两种交叉验证方法的精度均在1 K以内,证明了该方法的可行性,且基于光谱响应差异的验证方法精度更高.该研究为光学载荷在轨辐射定标的验证提供了理论基础. 相似文献
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本文提出了一种FPGA可编程逻辑单元中新型的查找表结构和进位链结构。查找表被设计为同时支持四输入和五输入的结构,可根据用户需要进行配置,且不增加使用的互连资源;在新型的进位链中针对关键路径进行了优化。最后在可配置逻辑单元中插入了新设计的可配置扫描链。该可编程逻辑单元电路采用0.13μm 1P8M 1.2/2.5/3.3V Logic CMOS工艺制造。测试结果显示可正确实现四/五输入查找表功能,且进位链传播前级进位的速度在同一工艺下较传统进位链结构提高了约3倍,同时整个可编程逻辑单元的面积较之前增大了72.5%。结果还显示,本文设计的FPGA在仅使用四输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7系列FPGA;在仅使用五输入查找表时,逻辑资源利用率高于Virtex II/Virtex 4系列FPGA。 相似文献
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基于H.264的可视电话软件开发 总被引:5,自引:2,他引:3
为了开发基于H.264标准的可视电话,采用高性能高速视频数字处理芯片(TMS320DM642)作视频编解码器,充分利用芯片的并行和流水处理功能,在单芯片上实现了视/音频编解码的并行实时处理,并达到可视电话实时通信要求. 相似文献
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Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology. 相似文献
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Haibing Yin Shizhong Li Honggang Qi Hongqi Hu 《Journal of Signal Processing Systems》2014,76(1):47-62
Motion vector (MV) prediction and residue coding technique is adopted to fully utilize the motion field redundancy in the prevailing video standards, and MV prediction is desired in both video encoder and decoder. The computation burden for MV prediction is not very high. However, there is high irregularity in raw MV prediction algorithm with two-stage and four-level hierarchical tree control flows. It makes efficient VLSI architecture implementation challenging. The high irregularity is mainly derived from the abundant inter prediction modes including variable block size partition and temporal prediction direction, as well as the irregular control flow of the MV prediction algorithm. This paper proposes a highly regular architecture to implement MV prediction for multi-standard video codec. Complex control logic is simplified by regularly table look-up of the control parameters predefined and stored in on-chip tables. The parameters of the current macroblock (MB) and its neighboring blocks are initialized and refreshed in a regular manner. Moreover, pipelining and parallelism are employed in the proposed architecture to improve throughput efficiency and tradeoff between hardware cost and efficiency. Simulation results verify the effectiveness of the proposed design. 相似文献
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以TMS320C6203为硬件平台,设计了高速G.729ab多通道声码器。使用纯汇编指令与C语言结合优化编程提高核心编解码算法效率,实时支持最大31个话路语音的G.729ab编解码。利用TMS320C6203的在片外设McBSP提供声码器连接PSTN的标准E1接口,设计了用于分组数据收发的RTP协议接口,利用TMS320C6203的HPI接口方式与上层处理器连接,使得声码器可灵活地应用于媒体网关。 相似文献
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Dinh A. Xiao Hu 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(6):745-750
This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a distance look-up table (DLUT). The concept of DLUT significantly reduces hardware requirements as this table eliminates the need for calculation circuitry. In addition, an output LUT (OLUT) is constructed based on the trellis diagram of the code. This table generates the decoding output using information provided by the algorithm. The use of this OLUT reduces the amount of storage requirement. The technique was used to design a 16-state, radix-4 codec for two-dimensional and four-dimensional TCM. The decoder was implemented in hardware after functional simulation. The tested ASIC has a core area of 1.1 mm/sup 2/ in 0.18-/spl mu/m CMOS. A decoding speed of 1 Gbps was achieved. Implementation results have shown that LUTs can be used to decrease hardware requirement and increase decoding speed. 相似文献