深亚微米SoC芯片物理设计中基于串扰的时序收敛方法

当芯片设计进入深亚微米，串扰效应引起大量的设计违规，尤其是对时序收敛产生很大的影响。实际上串扰对电路时序性能的影响非常难估计，它不仅取决于电路互联拓扑，而且还取决于连线上信号的动态特征。文章从串扰延时的产生原因开始分析，并提出了在O．18μm及以下工艺条件下对串扰延时进行预防．分析和修复的时序收敛方法。     

0.18μm CMOS工艺条件下的信号完整性分析

通过模拟分析了0 18μmCMOS工艺条件下的信号完整性问题.在进行串扰延迟和噪声分析中发现了一些规律,这些规律对以后的设计有一定的指导意义.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

一种抑制总线串扰的自适应时空编码方法

片上总线互连线间逐步增强的线间耦合效应加剧了总线信号串扰.本文根据互连线串扰模型,提出先传送奇数位信息,再传送偶数位信息,双时钟周期发送恶性串扰总线数据的自适应时间编码方法.在消除恶性串扰的同时,减小了总线自翻转能耗.并结合码本编码,获得一种自适应时空编码方法.仿真结果显示该方法的时间节省率达到30%以上,能耗节省率为4%～38%.对于32位数据总线,该方法仅需6根冗余线.     

一种低功耗抗串扰的自适应时空总线编码方法

深亚微米片上总线的功耗、布线面积约束和线间串扰是限制总线数据吞吐率的关键因素,为此该文提出一种自适应时空编码方法以降低总线的串扰延迟和功耗。该方法首先采用空间编码将总线分割为两个子总线,从而减小了恶性串扰发生几率;然后通过恶性串扰判决器分别判断子总线的原码数据及反码数据是否存在恶性串扰:对于任意子总线的原码数据与反码数据均存在恶性串扰的情况,传送屏蔽字;否则,选取无恶性串扰且动态功耗小的总线数据形式并传送。采用SPEC标准数据源对算法进行了评估,该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%,功耗比同类方法降低14.63%~54.67%,对于32位数据总线,仅需7根冗余线,在动态功耗、布线资源和性能方面获得了有效的优化。     

作波分复用AWG同频串扰的相关特性及理论研究

本文讨论了光信号在阵列波导光栅（AWG）中同频光电流串扰的自相关函数,从理论上探讨了同频串扰的自相关系数,研究了相关系数与同频串扰引起延时的关系,及同频串扰噪声功率和串扰的极化方向的关系,得到了相关系数R_F与AWG延时时间τ、记录值n之间的关系曲线.数值计算表明:串扰延时使AWG的传输信号存在负相关、弱相关、正相关,其串扰延时对记录长度的影响呈周期性变化.     

CMOS工艺多功能数字芯片的输出缓冲电路设计

为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试．提出了一种基于CSMC2P2M0．6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0．6μmCMOS工艺的工艺库（06mixddct02v24）仿真,基于CSMC2P2M0．6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW（多项目晶圆）计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。     

一种采用CMOS0．18μm制造的带EBG结构小型化的片上天线

采用标准0．18μmCMOS工艺设计制造了一种带EBG（电磁带隙）结构的小型化片上天线。该片上天线由一根长1．6mm的偶极子天线以及一对一维的尺寸240μm×340μmEBG结构构成。分别对该EBG结构以及片上天线的S11及S21进行了仿真和测试,结果表明该片上天线工作在20GHz,具有小型化的性能,同时具备三次谐波抑制的功能。     

片上网络的互连问题及解决措施综述

在大规模集成电路工艺的深亚微米时代,片上网络（NoC）互连总线遭遇了来自三个方面的威胁：功耗、传输延时、可靠性,它们已经成为限制NoC性能提高的瓶颈。鉴于总线编码的灵活性和综合处理能力,本文首先分析了多种分别针对功耗、延时、可靠性问题的总线编码处理方案,最后介绍了一种统一的总线编码框架来综合处理这三方面的挑战。     

Joint Equalization and Coding for On-Chip Bus Communication

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.     

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.     

基于ADS应用于GPS的低噪声放大器设计与仿真

设计了一种应用于GPS射频接收机中的单端低噪声放大器（LNA）,并利用安捷伦公司的ADS软件对电路进行了仿真。电路采用TSMC0．13μm工艺库模型,仿真结果表明在1．57GHz工作频率下,可以实现0．9dB的噪声系数和20dB的增益,较好的匹配（输入输出回波损耗S11,S22≤-20dB）,并且在1．2V电源电压下功耗仅为6mW。     

Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

With the scaling development of the minimum lithographic size, the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule. When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD imagepixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction, which results in pixel crosstalk. The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling. Some suppressed crosstalk methods have been reviewed. The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.     

基于DDR2控制器的主从结构DLL的研究与设计

提出了一种适用于DDR2控制器的主从结构的DLL的研究与设计,在不同的工艺、电压和温度（PVT）条件下,DLL所产生的时钟保证DDR2在读数据时,数据经过传输线传输后能被正确的采样;写数据时,DLL产生的时钟能精准地控制倍率转化。模拟仿真结果表明在0.13μm CMOS工艺下,该结构具有良好的性能特性,满足设计要求。该结构同样可用于其它需要固定延迟的电路。     

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-/spl mu/m TSMC CMOS technology and applied to a 4500-/spl mu/m long Metal4 bus. Circuit simulation results for different bus widths are presented.     

Low-power on-chip communication based on transition-aware global signaling (TAGS)

In this paper, we propose a new circuit structure, the transition aware global signaling (TAGS) receiver, that detects transitions at arbitrary switch points. The major performance advantage of this circuit occurs when it switches before the 50% point in the input transition. The TAGS receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Its ability to detect transitions before a standard inverter and locally generate them at its output, allows its use at the end of long interconnects with fewer repeaters for the same delay as the standard repeater paradigm. The need for fewer repeaters with the TAGS scheme results in lower power consumption for on-chip global communication, while also reducing the placement overhead involved with large buffer blocks. This is shown in the context of bus optimizations, where TAGS achieves up to 50% reduction in power compared to standard repeaters. In an industrial 0.13-/spl mu/m CMOS process, TAGS receivers enable 8-mm-long buses at 1.5-GHz clock rates without repeaters, while the traditional scheme required three repeaters on the line. An extensive analysis of crosstalk noise in the bus environment shows that TAGS can handle the noise levels produced in typical bus structures. Also, the variation of delay in the bus structure under worst-case power supply noise for the TAGS scheme is typically smaller than the delay variation using the standard repeater scheme.     

18μm CMOS工艺条件下的信号完整性分析

通过模拟分析了0.18μm CMOS工艺条件下的信号完整性问题.在进行串扰延迟和噪声分析中发现了一些规律,这些规律对以后的设计有一定的指导意义.     

用传输门VCO和动态PFD设计低功耗CMOS琐相环

锁相环（PLL）是VLSI系统的重要单元电路之一,为了实现高速低功耗的CMOS锁相环,用传输门VCO和动态反相器PFD电路设计CMOS锁相环。传输门结构VCO具有高速、低电压和低功耗的特性,而动态反相器PFD具有功耗低和面积小的特点。SPICE模拟表明,当电源电压为2．5V时,基于0．6μmCMOS工艺设计的CMOS锁相环电路,工作频率高达1000MHz,而功耗低于50mW。