Novel all-optical logic gate using an add/drop filter and intensity switch

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.     

Closed Cyclic DNA Machine for Sensitive Logic Operation and APE1 Detection

DNA self-assembly has been developed as a kind of robust signal amplification strategy, but most of reported assembly pathways are programmed to amplify signal in one direction. Herein, based on mutual-activated cascade cycle of hybridization chain reaction (HCR) and catalytic hairpin assembly (CHA), a closed cycle circuit (CCC) based DNA machine is developed for sensitive logic operation and molecular recognition. Benefiting from the synergistically accelerated signal amplification, the closed cyclic DNA machine enabled the logic computing with strong and significant output signals even at weak input signals. The typical logic operations such as OR, YES, AND, INHIBIT, NOR, and NAND gate, are conveniently and clearly executed with this DNA machine through rational design of the input and computing elements. Moreover, by integrating the target recognition module with the CCC module, the proposed DNA machine is further employed in the homogeneous detection of apurinic/apyrimidinic endonuclease 1 (APE1). The precise recognition and exponential signal amplification facilitated the highly selective and sensitive detection of APE1 with limit of detection (LOD) of 7.8 × 10⁻⁵ U mL⁻¹. Besides, the normal cells and tumor cells are distinguished unambiguously by this method according to the detected concentration difference of cellular APE1, which indicates the robustness and practicability of this method.     

A new universal gate for low power SoC applications

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels.     

Ultra-High bit rate all-optical AND/OR logic gates based on photonic crystal with multi-wavelength simultaneous operation

In this paper, a novel two-dimensional photonic crystal based all-optical AND/OR logic gates are designed, simulated and optimized. The structure is built on a linear square lattice photonic crystal platform. A multi-wavelength operation, together with a simultaneous operation, is achieved at ultra-high bit rates. The concurrent operation is attained without altering the proposed design continuously, as stated in the literature. It provides simplicity because there is no auxiliary input required along with the absence of externally attached phase shift units. The enhancement process has been done to the rod radius. A magnificent representation tool is developed. The benefit of the mentioned tool lies in the data combination of different operating wavelengths, contrast ratio, and bit rate; which will establish an efficient optimization process. Each gate is enhanced independently, then an overall improvement has been done. As a result, the operation at 1.52?µm will provide a successful multi logic gate operation with ultra-high bit rates of 6.76 and 4.74 Tbit/s for AND and OR logic gates, respectively. The design has an acceptable size of (19.8?×?12.6 µm) and a contrast ratio of 9.74?dB and 17.95?dB for the designed AND and OR gate, respectively. The design is highly sensitive to the waveguide length to verify the gates on demand.     

Heat Transfer in Fast Linear Annealing for Direct Bonding of SOI Wafer Pairs

A novel silicon-on-insulator (SOI) manufacturing method, the fast linear annealing (FLA) method, is proposed. In the fast linear annealing method, a halogen lamp moves with a constant speed above a silicon wafer pair prebonded by the hydrogen interaction. In order to optimize the processing parameters such as the initial heat treatment time and the moving speed of the halogen lamp, bonding strengths were measured when the moving speed varies in the range of 0.05–0.5 mm · s⁻¹. The temperature distribution of SOI is analyzed numerically by using a finite difference method. The SOI is modeled two-dimensionally, and the alternate direction implicit (ADI) technique is used for the calculation of the temperature. The calculation results show that the SOI reaches a steady-state temperature distribution in an elapsed time of 380 s of halogen lamp irradiation. The maximum temperature of SOI does not vary significantly as the moving speed of the halogen lamp increases. These results agree with the measurement results, which show that the bonding strength from the high-speed anneal (0.5 mm · s⁻¹) was of similar strength to that from the slow speed (0.05 mm · s⁻¹) process.Paper presented at the Seventh Asian Thermophysical Properties Conference, August 23–28, 2004, Hefei and Huangshan, Anhui, P. R. China     

Effects of two-photon absorption on pseudo-random bit sequence operating at high speed

The effect of two-photon absorption (TPA) on all-optical logic operation in quantum-dot semiconductor optical amplifier (QD-SOA) has been carried out. We model the rate equation with the TPA effect for the logic XOR gate, AND gate, and, for pseudo-random bit sequence (PRBS) generation. The simulated results indicate that the TPA induced pumping increases the output Q-factor (quality). The results show that the quality of the output depends on the input pulse width and the speed of operation. The PRBS system can operate at 250 and 320 Gb/s but an increase in pulse width decreases the output Q-factor.     

Demonstration of logic AND device using a split-gate pentacene field effect transistor

We report on the fabrication and performance of pentacene-based split-gate field effect transistors (FETs) on doped Si/SiO₂ substrates. Several transistors with split gate structures were fabricated and demonstrated AND logic functionality. The transistor’s functionality was controlled by applying either 0 or − 10 V to each of the gate electrodes. When − 10 V was simultaneously applied to both gates, the transistor was conductive (ON), while any other combination of gate voltages rendered the transistor highly resistive (OFF). A significant advantage of this device is that AND logic devices with multiple inputs can be built using a single pentacene channel with multiple gates. The p-type carrier mobility of charge within the pentacene active layer of these transistors was about 10^− 5 cm²/V-s. We attribute the low value of mobility primarily to the sharp contours of the pentacene film between the drain and the source contacts and to defects in the pentacene film. The average charge density was 1.4 × 10¹² holes/cm². Despite low mobility, the devices operated at lower drain-source (V_DS) and gate-source (V_GS) voltages as compared with previously reported pentacene based FETs.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Simple and universal platform for logic gate operations based on molecular beacon probes

A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements.     

Modelling,design and optimization of compact taper and gratings for mode coupling to SOI waveguides at C-band

In this work, the design and optimization of compact taper is presented to enable coupling of infrared light in the C-band with the nano-photonic silicon-on-insulator (SOI) integrated optical waveguide. The proposed compact taper results in ～96% transmission efficiency for the taper length of ～5?µm and ～99.5% transmission efficiency for the taper length of 10?µm. The use of the proposed compact taper significantly reduces the foot print of optical coupler (grating and proposed compact taper) to (10?×?5)?µm² with ～96% transmittance and (10?×?10)?µm² with ～99.5% transmittance. The end-to-end coupling loss is less than 0.01?dB in the C-band. The compact taper along with grating presented in this work can be used as an efficient optical coupler for mode coupling from fibre to SOI single-mode optical waveguide in high density optical integrated circuits operating at 1550?nm.     

Flexible logic gates composed of high performance GaAs-nanowire-based MESFETs with MHz-dynamic operations

High performance NOT, NAND and NOR logic gates composed of GaAs-nanowire (NW)-based metal-semiconductor field-effect transistors (MESFETs) were constructed on flexible plastics through a noble top-down route. The representative GaAs-NW-based MESFETs exhibited superior electrical characteristics such as a high mobility (～3300 cm(2) V(-) s(-1)), large I(on)/I(off) ratio (～10(8)) and small subthreshold swing (～70 mV/dec). The NOT, NAND and NOR logic gates showed a maximum voltage gain of 108 and logic swings of 97-99%. All of the logic gates successfully retained their electrical characteristics during 2000 bending cycles. Furthermore, the logic gates were well operated by square-wave signals of up to 100 MHz under various strain conditions. The high performances demonstrated in this study open the way to the realization of high speed flexible logic devices.     

High speed all-optical encryption and decryption using quantum dot semiconductor optical amplifiers

A scheme to realize high speed all-optical encryption and decryption using key-stream generators and an XOR gate based on quantum dot semiconductor optical amplifiers (QD-SOAs) was studied. The key used for encryption and decryption is a high speed all-optical pseudorandom bit sequence (PRBS) which is generated by a linear feedback shift register (LFSR) composed of QD-SOA-based logic XOR and AND gates. Two other kinds of more secure key-stream generators, i.e. cascaded design and parallel design, were also designed and investigated. Nonlinear dynamics including carrier heating and spectral hole-burning in the QD-SOA are taken into account together with the rate equations in order to realize all-optical logic operations. Results show that this scheme can realize all-optical encryption and decryption by using key-stream generators at high speed (~250 Gb/s).     

Study of all-optical logic XNOR gate based on XGM in linear optical amplifier

Future digital optical communication cannot develop without all-optical high-speed optical devices, especially in the field of high speed large capacity optical transmission, all-optical packet switching and optical computing, and thus optical logic devices are becoming a hotter spot of research. Based on the cross-gain modulation (XGM), a novel scheme of all-optical logic XNOR gate using linear optical amplifier (LOA) is presented in this paper. LOA results show a good gain characteristic, which can get better output logic operation than traditional semiconductor optical amplifier (SOA). Choosing suitable injection current, wavelength scope of the input signal and CW power can achieve better logic operation effect.     

Tunable Tribotronic Dual‐Gate Logic Devices Based on 2D MoS2 and Black Phosphorus

With the Moore's law hitting the bottleneck of scaling‐down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self‐powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual‐gate logic device based on a MoS₂ field‐effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm^–1. Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low‐power‐consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human–machine interfacing, data processing and transmission.     

Gate‐Controlled BP–WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics

p–n junctions play an important role in modern semiconductor electronics and optoelectronics, and field‐effect transistors are often used for logic circuits. Here, gate‐controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe₂) heterojunctions are reported. The gate‐tunable ambipolar charge carriers in BP and WSe₂ enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p–p and n–n) and anisotype (p–n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP–WSe₂ heterojunction diodes can be developed for high‐performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals.     

Responsive interface switchable by logically processed physiological signals: toward "smart" actuators for signal amplification and drug delivery

Biomarkers characteristic of liver injury, alanine transaminase and lactate dehydrogenase, were processed by an enzyme-based system functioning as a logic AND gate. The NAD+ output signal produced by the system upon its activation in the presence of both biomarkers was then biocatalytically converted to a decrease in pH. The acidic pH value biocatalytically produced by the system as a response to the biomarkers triggered the restructuring of a polymer-modified electrode interface. This allowed a soluble redox species to approach the electrode surface, thus switching the electrochemical reaction ON. The redox transformations activated by the biochemical signals resulted in an amplification of signals. This system represents the first example of an integrated sensing-actuating chemical device with the implemented AND Boolean logic for processing natural biomarkers at their physiologically relevant concentrations.     

Crossed-film cryotron switching speed

To date there have been no direct measurements of the switching speed of an individual crossed-film cryotron (CFC) due to the extremely low gate resistance of the device in its normal state. A method which is, in principle, similar to conventional sampling techniques is used to determine the CFC switching speed with a 2-ns time resolution and a gate resistance sensitivity of 0.1 μΩ. CFC switching speeds are determined as a function of control current overdrive and gate current. In this way, the gain-bandwidth limitations of the device are experimentally determined. These data can be used to determine the optimum speeds of CFC logic circuits.     

Gate‐Tunable and Multidirection‐Switchable Memristive Phenomena in a Van Der Waals Ferroelectric

Memristive devices have been extensively demonstrated for applications in nonvolatile memory, computer logic, and biological synapses. Precise control of the conducting paths associated with the resistance switching in memristive devices is critical for optimizing their performances including ON/OFF ratios. Here, gate tunability and multidirectional switching can be implemented in memristors for modulating the conducting paths using hexagonal α‐In₂Se₃, a semiconducting van der Waals ferroelectric material. The planar memristor based on in‐plane (IP) polarization of α‐In₂Se₃ exhibits a pronounced switchable photocurrent, as well as gate tunability of the channel conductance, ferroelectric polarization, and resistance‐switching ratio. The integration of vertical α‐In₂Se₃ memristors based on out‐of‐plane (OOP) polarization is demonstrated with a device density of 7.1 × 10⁹ in.^?2 and a resistance‐switching ratio of well over 10³. A multidirectionally operated α‐In₂Se₃ memristor is also proposed, enabling the control of the OOP (or IP) resistance state directly by an IP (or OOP) programming pulse, which has not been achieved in other reported memristors. The remarkable behavior and diverse functionalities of these ferroelectric α‐In₂Se₃ memristors suggest opportunities for future logic circuits and complex neuromorphic computing.     

Thermal AND Gate Using a Monolayer Graphene Nanoribbon

The first ever implementation of a thermal AND gate, which performs logic calculations with phonons, is presented using two identical thermal diodes composed of asymmetric graphene nanoribbons (GNRs). Employing molecular dynamics simulations, the characteristics of this AND gate are investigated and compared with those for an electrical AND gate. The thermal gate mechanism originates through thermal rectification due to asymmetric phonon boundary scattering in the two diodes, which is only effective at the nanoscale and at the temperatures much below the room temperature. Due to the high phonon velocity in graphene, the gate has a fast switching time of ≈100 ps.     

Cascading Wafer-Scale Integrated Graphene Complementary Inverters under Ambient Conditions

The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, A(v) ～ -5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concern, similar to emitter-coupled logic.