Optimization of photo‐aligned ferroelectric liquid‐crystal display under passively addressed driving

Abstract— A ferroelectric liquid‐crystal (FLC) passively addressed 64 × 64 display based on the photo‐alignment technique has been developed. The display matrix has dimensions of 33 × 33 mm², and the FLC layer thickness is about 5 μm. Asymmetric boundary conditions, when only one of ITO surfaces of the display matrix is covered with the photo‐aligning layer while another one is not, have been used for providing both high contrast ratio and steady multiplex operation. The electro‐optical performance of the 5‐μm FLC display is presented, including bistable switching in static operation, optimization in multiplexing operation, and gray‐scale generation.     

Multistable electro‐optical modes in ferroelectric liquid crystals

Abstract— Multistable electro‐optical modes exist under certain conditions in ferroelectric liquid‐crystal (FLC) cells, which means that any light‐transmission level can be memorized after the driving voltage is switched off. The multistability is responsible for three new electro‐optical modes with different shapes of the gray‐scale curve that can be either S‐shaped (double or single dependent upon the applied‐voltage pulse sequence and boundary conditions) or V‐shaped dependent upon boundary conditions and FLC cell parameters. The origin of these modes will be described.     

Electro‐optic properties of an intrinsic half‐V‐mode FLCD and its application to field‐sequential full‐color LCDs using a poly‐Si TFT matrix array

Abstract— An intrinsic half‐V‐mode ferroelectric liquid‐crystal display (FLCD) exhibiting a high contrast ratio (300:1), owing to defect‐free gray‐scale capability, with a high response speed (τ ? 400 μsec) and good switchability with TFTs, has been developed. Furthermore, this FLCD features high‐temperature reliability owing to the use of a special hybrid alignment technique. We successfully fabricated an active‐matrix poly‐Si TFT field‐sequential full‐color (FS FC) LCD with XGA specifications and a 0.9‐in. diagonal using a half‐V‐mode FLCD and an RGB light‐emitting‐diode (LED) array microdisplay. It is shown that the fabricated active‐matrix FS FCLCD exhibits good moving‐image performance with high full‐color display capability.     

Use of self‐erase discharges for high‐speed and low‐voltage addressing of PDPs

Abstract— A technique called “self‐erase‐discharge addressing” has been incorporated with a address‐while‐display driving scheme, contiguous subfield, and erase addressing to obtain high‐speed and low‐voltage addressing of PDPs. The technique uses a relatively high X‐sustain pulse voltage VXsus, which produces a weak self‐erase discharge at its trailing edge. An application of a data pulse Vdata synchronous to a weak self‐erase discharge results in full erase discharge and eliminates all the wall charges. The technique assures a wider operating‐voltage margin since it provides identical amounts of priming charges as well as wall charges to all the horizontal scan lines just prior to addressing. The priming charges are generated by the weak self‐erase discharges, resulting in low Vdata of 30 V and a high addressing speed of 0.66 μsec for a Ne + 10% Xe PDP. V_Xsus = 245 V, and the voltage margins of Vdata and VXsus were 35 and 16 V, respectively. For a 30% Xe PDP, Vdata and VXsus were 30 and 335 V, respectively, with an addressing speed of 1.0 μsec. In order to obtain high dark‐room contrast, it is essential to use ramp reset pulses, with which erase addressing cannot be achieved. By adopting the write addressing only to the first subfield and the self‐erase‐discharge addressing to the subsequent subfields, a peak and background luminance in green of 3100 and 0.22 cd/m², respectively, were obtained with a dark‐room contrast of 14,000:1. The number of subfields was 28, and the light emission duty was 83%. The number of ramp reset pulse drivers could be reduced to 12 by adopting the common reset pulse technique.     

Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

Poststress RF‐drifts of dual‐band LC VCO in 0.18‐μm CMOS technology

This article studies the RF‐property of a dual‐band voltage‐controlled oscillator (VCO). The designed circuit consists of a dual‐resonance LC resonator and a Colpitts negative resistance cell. The dual‐resonance LC resonator comprises a series‐tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology. The VCO can generate differential signals in the frequency range of 3.0–3.37 GHz and 6.95–7.40 GHz with core power consumption of 10.08 and 10.24 mW at the dc drain‐source bias V_DD of 1.4 V, respectively. The die area of the dual‐band VCO is 0.485 × 0.800 mm². The circuit was operated at V_DD = 3 V for 8 h and significant drift in RF parameters was found. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:243–248, 2014.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Optical response of helix‐free FLC: Continuous gray scale,fastest response,and lowest control voltage

Electro‐optical response of a display cells with novel helix‐free FLC (differently, compensated helix ferroelectric—CHF) is considered. Predominance of the shear viscosity in the soliton mode of FLC director reorientation leads to weakening the temperature dependence of the response time. Increasing the electric field frequency expands this temperature interval, and it is 15°C… 45°C for the frequency about 3 kHz at ±1.5 V in a display cell with FLC viscosity of 0.7 P. Increasing the rotational viscosity up to 1.0 P provides the increase of speed ability due to Maxwell's nature of energy dissipation. The optical response time of 24 µs and light modulation frequency of 7 kHz were achieved at the amplitude of control voltage pulses ±1.5 V. Thus, like NLC based cells, the experimental samples of CHF based display cells at the same (or even lower) value of voltage and electric field tension (1–2 V/µm) show the continuous gray scale and hysteresis‐free modulation characteristic (up to 5 kHz) but can provide 40–50 times (!) higher speed. These break‐through results characterize CHF as the most high‐speed materials for future 3D displays and displays using field sequential color technique, including FLCoS and TFT addressed, as well as displays with new functional properties.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.     

A low‐cost low‐temperature thin‐film‐transistor backplane based on oxide semiconductor

Abstract— An indium‐gallium‐zinc‐oxide (IGZO) thin‐film transistor (TFT) based on an anodized aluminum‐oxide gate dielectric and photoresist passivation has been fabricated. The TFT showed a field‐effect mobility of as high as 18 cm²/V‐sec and a threshold voltage of only 0.5 V. A 50 × 50 AMOLED display based on this type of TFT was designed and fabricated. The average luminance of the panel was 150 cd/m², and the maximum pixel luminance was 900 cd/m².     

High‐performance polymer‐stabilized blue‐phase LCD with low driving voltage

We have developed a polymer‐stabilized blue‐phase LCD in which the diffraction wavelength of blue‐phase liquid crystal is in the ultraviolet region and which is driven at a low voltage of V₁₀₀ = 27 V. Prototypes of 3.4‐in polymer‐stabilized blue‐phase LCDs were made, which include a highly reliable crystalline oxide semiconductor. We succeeded in fabricating not a test cell but a display having a contrast ratio higher than 1000 : 1 for the first time in the world.     

A 5‐in. flexible ferroelectric liquid‐crystal display driven by organic thin‐film transistors

Abstract— An organic thin‐film‐transistor (OTFT) driven color flexible ferroelectric‐liquid‐crystal (FLC) display with 160 × 120 pixels and a resolution of 50 ppi has been developed. The flexible FLC was fabricated on a pentacene‐OTFT array using printing and lamination techniques. To drive the display at a fast driving speed, an OTFT was developed with a short channel length having a large current output. The fabricated OTFT array with a channel length of 5 μm exhibits a carrier mobility of 0.3 cm²/V‐sec and an ON/OFF ratio of over 10⁷ at a low drain voltage of ?6 V. A field‐sequential‐color system with a flexible backlight unit was also developed and used to drive the display. Color moving images were successively shown on the 5‐in. display using an active‐matrix driving technique of the OTFT.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Flexible AMOLED displays on stainless‐steel foil

Abstract— The world's thinnest flexible full‐color 5.6‐in. active‐matrix organic‐light‐emitting‐diode (AMOLED) display with a top‐emission mode on stainless‐steel foil was demonstrated. The stress in the stainless‐steel foil during the thermal process was investigated to minimize substrate bending. The p‐channel poly‐Si TFTs on stainless‐steel foil exhibited a field‐effectmobility of 71.2 cm²/N‐sec, threshold voltage of ?2.7 V, off current of 6.7 × 10¹³ A/μm, and a subthreshold slope of 0.63 V/dec. These TFT performances made it possible to integrate a scan driver circuit on the panel. A top‐emission EL structure was used as the display element, and thin‐film encapsulation was performed to realize a thin and flexible display. The full‐color flexible AMOLED display on stainless‐steel foil is promising for mobile applications because of its thin, light, rugged, and flexible properties.     

Annealing effect of low‐temperature (<150°C) Cat‐CVD gate dielectric silicon nitride films diluted with atomic hydrogen

Abstract— The effect of in‐situ hydrogen pretreatment on dielectric properties of silicon nitride (SiN^x) thin films for a gate dielectric layer has been studied. SiN^xthin films were grown at a low temperature (150°C) by Catalytic CVD followed by conventional furnace annealing at 150°C for 2 hours. The in‐situ hydrogen pretreatment was performed without vacuum break before the sample was transferred to the furnace for thermal annealing. Capacitance—voltage (C‐V) and current‐density—voltage (J‐V) measurement showed that the hydrogen pretreatment was effective in reducing the hysteresis in the C‐V curve and in increasing the breakdown voltage. Without the treatment, the 150°C annealing failed to produce reliable C‐V and I‐V characteristics. The C‐V hysteresis and the threshold voltage shift of SiN^x were improved by furnace annealing as the hydrogen dilution ratio increased. Also, addition of hydrogen to the deposition gas mixture helped to improve the dielectric properties of the SiN^x films after thermal annealing. The combination of hydrogen dilution of the source gas and the in‐situ hydrogen treatment was successful in producing low‐temperature SiN^x films applicable to a‐Si TFTs. The TFT fabricated by using these films showed a field‐effect mobility of 0.23 cm²/V‐sec and a Vth of 3.1 V.     

Ten switched‐beams with 2 × 2 series‐fed 2.4 GHz array antenna and a simple beam‐switching network

This article presents a 2 × 2 series fed 2.4 GHz patch antenna array having multiple beam switching capabilities by using two simple 3 dB/90° couplers to achieve required amplitude and phase excitations for array elements with reduced complexity, cost and size. The beam switching performance with consistent gain and low side lobe levels (SLL) is achieved by exciting the array elements from orthogonally placed thin quarter‐wave (λ_g/4) feeds. The implemented array is capable to generate ten (10) switched‐beams in 2‐D space when series fed elements are excited from respective ports through 3 dB quadrature couplers. The dual polarized characteristics of presented array provide intrinsic interport isolation between perpendicularly placed ports through polarization diversity to achieve independent beam switching capabilities for intended directions. The implemented antenna array on 1.575 mm thick low loss (tan δ = 0.003) NH9450 substrate with ε_r = 4.5 ± 0.10 provides 10 dB return loss impedance bandwidth of more than 50 MHz. The measured beam switching loss is around 0.8 dB for beams switched at θ = ±20°, Ф = 0°, 90°, and 45° with average peak gain of 9.5 dBi and SLL ≤ ?10 dB in all cases. The novelty of this work is the capability of generating ten dual polarized switched‐beams by using only two 3 dB/90° couplers as beam controllers.     

Characteristics of a‐IZO TFTs with high‐κ HfSiOx gate insulator annealed in various conditions

In this work, we investigate the enhanced performance of amorphous indium zinc oxides‐based thin film transistors with hafnium silicate (HfSiO_x) gate insulators. HfSiO_x gate insulators annealed at various conditions are deposited by cosputtering of hafnium oxide and Si. The structural properties of HfSiO_x are investigated using the atomic force microscopy, X‐ray diffraction, and x‐ray photoelectron spectroscopy (XPS). techniques. Furthermore, the electrical characteristics of HfSiO_x are analyzed to investigate the effect of annealing conditions. We obtain optimal results for thin film transistors with HfSiO_x gate insulators annealed for 1 h at 100 °C, with a saturation mobility of 1.2 cm²/V · s, threshold voltage of 2.2 V, on current/off current ratio of 2.0 × 10⁶, and an insulator surface roughness of 0.187 nm root mean square.     

Flexible color LCD panel driven by low‐voltage‐operation organic TFT

Abstract— A flexible color LCD panel driven by organic TFTs (OTFTs) was successfully demonstrated. A pentacene OTFT with an anodized Ta₂O₅ gate insulator, which can be operated at low voltage, was developed. In order to improve the electrical performance of the OTFT, the gate insulator was surface treated by processes such as O₂ plasma, UV light irradiation, and hexamethyldisilane treatments. The fabricated OTFT exhibited a mobility of 0.3 cm²/V‐sec and a current on/off ratio of 10⁷ with a low operating drain voltage of ?5 V. A fast‐response‐time flexible ferroelectric LCD, which contains polymer networks and walls, was integrated with the OTFTs by using a lamination and a printing technique. As a result, color images were achieved on the fabricated panel by using a field‐sequential‐color method at a low driving voltage of less than 15 V_pp.     

An active‐matrix organic light‐emitting‐diode pixel circuit for the compensation of I × R voltage drop in power line

Abstract— A new voltage‐driving active‐matrix organic light‐emitting diode (AMOLED) pixel circuit is proposed to improve the display image‐quality of AMOLED displays. Because OLEDs are current‐driven devices, the I × R voltage drop in the power lines is evitable. Accordingly, the I × R voltage‐drop compensation scheme should be included in the pixel‐driving method when a voltage‐compensation method is used. The proposed pixel was designed for the compensation of an I × R voltage drop in the power lines as well as for the compensation of the threshold‐voltage non‐uniformity of low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS TFTs). In order to verify the compensation ability of the proposed pixel, SPICE simulation was performed and compared with those of other conventional pixels. When the Vss voltage varies from 0 to 1 V, the drain current of the proposed pixel decreased by under 1% while that of conventional Vth compensation methods without Vss compensation decreased by over 60%. 2.2‐in. QCIF⁺ full‐color AMOLED displays, which employ the proposed pixel, have been also developed. It was verified by comparison of the display image quality with a conventional panel that our proposed panel successfully overcame the voltage‐drop problems in the power lines.