基于多阈值技术的超低功耗电路设计

随着工艺进入深亚微米阶段,漏电流带来的静态功耗已经成为不可忽视的部分。多阈值CMOS技术是一种降低电路漏电流功耗的有效方法。本文在延迟不敏感异步电路中应用多阈值CMOS技术,该设计能显著的降低功耗,同时解决了同步电路存在的问题,比如sleep信号的产生,存储元件在sleep模式下数据丢失。这对深亚微米低功耗电路的设计具有一定的实际意义。     

降低集成电路漏电流功耗的电路设计技术

目前半导体技术发展日新月异,集成电路工艺已经低于30nm,工作频率也高达2GHz以上,此时CMOS电路的静态功耗在总功耗中所占的比例也变得可观,这对功耗控制就提出了更高的要求。本文主要介绍降低集成电路漏电流功耗的几种方法。以反向器为例,针对其中的多阈值CMOS、可变阈值CMOS和强制晶体管堆栈的设计方法用HSPICE进行了仿真模拟,比较不同方法的效果和对电路的影响。     

低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。     

应用输入向量控制技术降低漏电功耗的快速算法

随着工艺的发展,为保证电路的性能和噪声容限必须降低阈值电压,这将导致漏电流呈指数增长,漏电功耗因而将逐渐超过动态功耗占据主导地位. CMOS的堆栈效应导致电路在不同向量下的静态功耗不同,因此在电路进入睡眠状态时使用输入向量控制技术是一种低功耗设计的有效方法,如何快速找到一个可降低电路漏电功耗的向量就成了问题的关键.介绍了一种在给定向量集合中查找低功耗向量的快速算法——基于概率传递的标记算法,并为此开发了一个事件驱动的门级组合电路仿真器.通过对ISCAS和龙芯处理器电路的实验结果表明,该算法同传统方法比较可以提高性能3.4倍,误差率仅约0.14%.     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

基于输入向量控制的衬底偏置技术面积优化方法

随着集成电路工艺进入纳米时代,VLSI漏电功耗迅速增加,增加了实时功耗管理系统的面积开销.为了大幅度减小反向衬底偏置(RBB)控制管的面积,对广泛应用的RBB优化漏电流技术提出一种新方法.基于双阈值CMOS电路设计,在输入最小漏电流向量的条件下,仅将反向偏置电压VRBB加到处于决定态的低阈值电压MOS管上,通过大幅度减小应用VRBB的晶体管数量来降低VRBB控制管的面积开销.在基于22nm工艺ISCAS85基准电路上与单纯RBB方法进行比较的实验结果表明,该方法以损耗27. 94%的漏电功耗优化效果为代价,降低了84. 91%的面积开销.     

DSP程序地址总线低功耗分段Gray编码方法

地址总线的功耗是DSP功耗的重要来源。降低地址总线上的翻转率可以有效降低整个系统的功耗。文章在分析CMOS电路功耗基础上,提出了一种改进的Gray编码。结果表明,采用此种编码可以有效地降低DSP程序地址总线功耗。     

基于亚阈值漏电流的数据Cache低功耗控制策略研究

随着工艺尺寸及处理器频率的提高,Cache的功耗已经成为处理器功耗的重要来源,数据Cache的亚阈值漏电流功耗在总功耗中的比重也在上升;提出一种通过降低未被访问的Cache line的亚阈值漏电流功耗来降低整个数据Cache功耗的控制策略;该策略对所有Cache line周期性地提供低电压,从而降低了SRAM单元的亚阈值漏电流;当某一行被访问时,提供正常的电压,直到下一次被周期性地控制提供低电压;仿真结果显示,此策略以较少的硬件代价和访问延迟显著地降低了数据Cache的亚阈值漏电流功耗。     

一种有效的低功耗扫描测试结构——PowerCut

扫描测试是超大规模集成电路测试中最常用的一种技术.但在扫描测试过程中,扫描单元的频繁翻转会引起电路中过大的测试功耗,这对电路测试提出了新的挑战.提出了一种新颖的低功耗全扫描结构——PowerCut,通过对扫描链的修改,加入阻隔逻辑,有效降低扫描移位过程中的动态功耗,同时加入控制单元,使电路在扫描移位过程时进入低漏电流状态,降低了电路的静态功耗.实验表明该结构在较小的硬件开销范围内有效地减小了扫描测试功耗.     

基于功耗敏感性的降低嵌入式电路功耗方法

研究降低嵌入式系统的功耗问题。由于频繁进行电容充放电,以及晶体管瞬间导通所产生的动态和静态消耗过大,传统的嵌入式硬件系统中,大规模CMOS电路在工作状态切换存在电路的功耗过高的缺点。为解决上述问题,提出通过对动态功耗和静态功耗的产生及功耗模型进行研究,采用功耗敏感性分析的嵌入式降低功耗方法,通过分析电路的功耗敏感度,设计出功率消耗较低的电路,克服传统方法的弊端。实验表明,改进方法能够大幅降低嵌入式CMOS电路的消耗功率,取得了很好的效果,为设计提供了依据。     

Leakage Minimization Technique for Nanoscale CMOS VLSI

Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.     

Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.     

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation.Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor(CMOS)circuits during test has become a significant part of the total power dissipation.Hence,it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test,to increase test reliability and to reduce test cost.This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it,we propose techniques based on don't care bits(denoted by Xs)in test vectors to optimize leakage current in integrated circuit(IC)test by genetic algorithm.The techniques identify a set of don't care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector(MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.     

Leakage Current Optimization Techniques During Test Based on Don t Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,     

Leakage current estimation of CMOS circuit with stack effect

Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.     

Leakage reduction in dual mode logic through gated leakage transistors

This contribution proposes a technique for leakage power reduction in Dual Mode Logic (DML) circuits by incorporating Gated Leakage Transistor (GLT). The resulting circuits are named as GALEOR with Dual Mode Logic (GDML). Further, GDML design is extended by including a footed diode transistor, the design so obtained is referred to as GALEOR with Dual Mode Logic with footed diode (GDMLD). The analysis is done using footed type A and type B DML gates, resulting in GDML and GDMLD variants referred to as GDML-TA, GDML-TB, GDMLD-TA and GDMLD-TB. Two input NAND and NOR gates along with a full adder and a 2-bit multiplier circuit are used to investigate the proposed techniques at 90 nm and 45 nm technology nodes in both static and dynamic mode using SymicaDE tool. Analysis of leakage power reveals that its value increases with technology scaling. Average leakage power saving is 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD in static mode. Similarly, in pre-charge phase of dynamic mode, this value varies from 5.47%-28.22% for GDML and 14.55%-77.51% for GDMLD. For evaluation phase, average leakage power saving of 44.69%-74.11% for GDML and 67.18%-90.76% for GDMLD is achieved. Analysis of delay reveals that both the techniques increase delay of the design while providing significant leakage power saving.     

片内二级Cache的静态功耗优化技术研究

随着集成电路制造工艺进入超深亚微米阶段,静态功耗在微处理器总功耗中所占的比例越来越大,尤其是片上二级Cache。在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化静态功耗成为业界研究的热点。本文提出了一种ADSR算法,在保证处理器性能不受影响的前提下,可以大幅降低二级Cache的静态功耗。