Low-power video encoder/decoder chip set for digital VCRs

This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm² and 79 mm² die, respectively     

基于IMX53的视频编码的研究与应用

视频信号数字化后的海量数据,对信息存储和网络通信提出了更高的要求,因此需要对视频数据进行压缩编码。对VPU的硬件结构和内部工作流程、VPU的接口控制、API软件控制以及基于API函数对视频编码的应用程序设计进行了详细介绍,通过基于API函数的应用程序调用VPU模块,对像素分别为1 280×720和352×288的YUV格式原始视频序列进行H.264标准硬件编码实验,得出VPU的编码性能参数。实验结果表明,VPU模块能够对多种分辨率的YUV格式视频序列进行高效的H.264标准的压缩编码,并且编码的速率也很高,最高可对帧频为30 fps的1 280x720像素高清视频进行实时的压缩编码。     

Focal-Plane Spatially Oversampling CMOS Image Compression Sensor

Image compression algorithms employ computationally expensive spatial convolutional transforms. The CMOS image sensor performs spatially compressing image quantization on the focal plane yielding digital output at a rate proportional to the mere information rate of the video. A bank of column-parallel first-order incremental DeltaSigma-modulated analog-to-digital converters (ADCs) performs column-wise distributed focal-plane oversampling of up to eight adjacent pixels and concurrent weighted average quantization. Number of samples per pixel and switched-capacitor sampling sequence order set the amplitude and sign of the pixel coefficient, respectively. A simple digital delay and adder loop performs spatial accumulation over up to eight adjacent ADC outputs during readout. This amounts to computing a two-dimensional block matrix transform with up to 8times8-pixel programmable kernel in parallel for all columns. Noise shaping reduces power dissipation below that of a conventional digital imager while the need for a peripheral DSP is eliminated. A 128times128 active pixel array integrated with a bank of 128 DeltaSigma-modulated ADCs was fabricated in a 0.35-mum CMOS technology. The 3.1 mm times 1.9-mm prototype captures 8-bit digital video at 30 frames/s and yields 4 GMACS projected computational throughput when scaled to HDTV 1080i resolution in discrete cosine transform (DCT) compression     

An ultra low power adaptive wavelet video encoder with integratedmemory

This paper describes a low-power, single-chip video encoder intended for battery-operated portable applications. Design goals are minimizing system power as well as utilized bandwidth, and maximizing system integration. The encoder achieves competitive compression, with convenient bit rate scalability, using a peak power dissipation of several hundred μW on a video stream of 8-bit gray scale, 30 frame/s, and 128×128 demonstration resolution. Compression is performed using wavelet filtering, zero-trees, and arithmetic coding, all integrated on a single chip (3 million transistors, 1 cm², in 0.6 μm CMOS, operating at 500 kHz), with no external memory or control. Results do not include use of motion compensation, however, hooks are included at algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher, and more internal memory. In the absence of motion compensation, temporal correlation is still utilized through the use of simple frame differencing. The architectural centerpiece is a massively parallel, fine granularity SIMD array of processing elements (PEs). A mapping is made between small image blocks (4×4 pixels on the test chip) and PEs, with each PE containing both memory and logic required for its block. These results are obtained by careful coordination of design in a deep vertical manner, ranging from system, algorithmic, architectural, circuit, and layout, and designing simultaneously for all required algorithmic subcomponents     

基于C64x DSP的MPEG-4视频编码器算法设计及优化

本文介绍了在TI C64x DSP平台上实现MPEG-4 Simple Profile视频编码器的算法设计与优化方法。算法上,重点对运动估计进行了改进及优化,在图像质量(PSNR)损失较小的情况下,大大降低了计算复杂度。根据C64x DSP的特性,对整个编码器的程序结构和主要计算模块进行结构级的优化,主要包括增强存储器访问效率及提高代码并行性。实验结果表明,对CIF大小的视频序列,该编码器具有100fps以上的编码速度,可以在C64x DSP上实现多路视频编码。     

A charge-coupled area image sensor and frame store

A two-dimensional three-phase charge-coupled array with 128 × 106 elements, that can serve either as a solid-state image sensor or as an analog serial memory, has been built. As an image sensor the device has been operated successfully in the frame transfer mode to yield 120 frames/s with 64 × 106 resolution elements. By using the whole array as an image sensor, pictures with 128 × 106 resolution elements have been obtained at 15 frames/s with tolerable smearing. In the memory mode the device can store a whole analog frame as produced by a companion device, or 13 568 bits of digital information. But for the latter application defect-free devices are mandatory. The design of the device, the various modes of operation, the quality of the results, some typical defects, and some further applications are discussed.     

High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter

This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet the real time constraint of the deblocking filter algorithm for the 16:9 video format (4690$,times,$ 2304) at 30 frames per second (fps) at 200-MHz clock rate.      

Adaptive predictive coding for newspaper facsimile

An adaptive predictive coding method, which efficiently encodes newspaper pages with printed text and screened photographs is presented. This coding technique utilizes two kinds of predictors with different reference picture elements (pels). One is applied to printed text and the other is applied to screened photographs. The Dth previous pel and its neighboring pels age adopted as the reference pels for the photograph predictor, where distance D coincides with the screen period. Comparing the adaptive predictive coding with a typical document facsimile coding, the data compression ratio is improved by about two times for a screened photograph (compression ratio is 5 ∼ 6) and is almost the same or slightly higher for printed text. Computer simulation shows that if a 500-kbits buffer memory is employed, it is possible to transmit most pages, including an extreme case of a 100 percent photograph page, with a 4500-rev/min scanner at a transmission bit rate of 128 kbit/s. For average pages the revolution speed can be raised to 6000 rev/min. Page transmission time of about 5 min in analog facsimile through a 48-kHz band can be reduced to 1.8 min by adopting the digital transmission with a 128-kbit/s data modem and the adaptive predictive coding technique, when the facsimile revolution speed is set at 6000 rev/min.     

A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems

We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process complete image frames. The neuromorphic cortical-layer processing microchip presented in this paper computes convolutions of programmable kernels over the AER visual input information flow. It not only computes convolutions but also allows for a programmable forgetting rate, which in turn allows for a bio-inspired coincidence detection processing. Kernels are programmable and can be of arbitrary shape and arbitrary size of up to 32 times 32 pixels. The convolution processor operates on a pixel array of size 32 times 32, but can process an input space of up to 128 times 128 pixels. Larger pixel arrays can be directly processed by tiling arrays of chips. The chip receives and generates data in AER format, which is asynchronous and digital. However, its internal operation is based on analog low-current circuit techniques. The paper describes the architecture of the chip and circuits used for the pixels, including calibration techniques to overcome mismatch. Extensive experimental results are provided, describing pixel operation and calibration, convolution processing with and without forgetting, and high-speed recognition experiments like discriminating rotating propellers of different shape rotating at speeds of up to 5000 revolutions per second     

Real-time video decoding scheme for HDTV set-top boxes

We present a scheme for real-time digital HDTV video decoding suitable for DVB or ATSC set-top boxes. Our technique is based on a dual decoding datapath controlled in two fixed-scheduling combinations with an efficient memory interface scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on a video format of 1920 /spl times/ 1080 pixels/frame at 30 frames/s, at a bit rate of 18-22 Mbps.     

高清晰度电视芯片中视频和音频同步的异步实现

高清晰度电视的传输流采用了MPEG－2系统层标准ISO／IEC 13818－1。阐述了高清晰度电视（HDTV）传送流中时间信息码在视频和音频同步中的作用，分析了信源解码器中视频和音频同步的原理。就实际芯片中系统时钟的恢复，视频和音频的跳帧等机制进行了讨论，并提出了一种非锁相异步全数字视音同步实现方案。该方案采用了直接置数法恢复系统时钟,滞后跳帧法实现视频与系统时钟的同步，数字锁相法控制音频与系统时钟同步，最后，对视频帧率和音频PCM时钟的偏差等问题作了进一步的探讨。     

视频解码系统中读写带宽压缩算法设计

随着人们更多地使用携带式消费电子产品,电子产品中的电力消耗问题已经渐渐成为视频编解码器设计中关注的最主要的设计问题.特别是在最新的编码标准H.264/AVC中,由于采用了多种新的先进的压缩策略,编码器达到了更高的压缩效率的同时,由于这些新的性能,使H.264/AVC的解码器需要对外部存储进行大量的读取.所以,内存读取带宽成为对于整个系统成本的关键问题,具体如在使用电池提供高清视频播放的消费者电子产品中,需要以更低的电力提供更好更长时间的视频.在这个研究中,提出了针对于视频压缩解码系统中内存读写带宽问题所设计的可调的参考帧压缩算法设计的方案,通过降低系统读取外部内存的带宽而达到降低视频解码系统电力消耗的目的.     

基于OpenRISC1200的H.264视频解码器片上系统设计

新一代的压缩标准H.264以其高压缩率与高图像质量而备受青睐,将H.264集成于SoC(片上系统Sys-tern on chip)已成为必然的发展趋势.基于开源免费的32位OpenRISC1200 CPU,设计了H.264解码器SoC系统,系统以OpenRISC1200为核心控制模块,其他所有外围模块包括H.264解码...     

基于DSP的视频采集存储系统设计

介绍了视频采集存储系统的硬件设计及主要模块的数据处理流程、系统测试结果。采集制式为PAL的视频信号。经过视频解码器TVP5150转换为数字视频数据,利用TMS320DM642和CPLD器件及与非门Flash等主要器件实现了集视频数据采集、以太网传输、存储、压缩于一体的视频处理系统,该系统可用于工业流程检测、智能交通、机器人巡逻等涉及运动图像处理的领域。     

嵌入式远程视频监控系统的设计与实现

以S3C2410嵌入式处理器为核心,通过嵌入式多任务操作系统Linux采集摄像头视频数据,视频数据经JPEG算法压缩后通过网络实现远程传输。系统硬件主要包括CPUS3C2410、2片16Mx16型号为K4S561632C的SDRAM内存和16MByte型号为E28F128J3A150的NOR Flash固态存储器。系统软件设计主要包括构建ARM-Linux嵌入式软件平台．视频图像采集、压缩和网络传输的实现。实验表明,该设计达到预期目标,满足系统实时性要求,与传统PC机的监控系统相比,体积和成本分别减少75％和60％以上。     

MPEG-2 video compression

MPEG-2 is an extension of the MPEG-1 international standard for digital compression of audio and video signals. MPEG-1 was designed to code progressively scanned video at bit rates up to about 1.5 Mbit/s for applications such as CD-I (compact disc interactive). MPEG-2 is directed at broadcast formats at higher data rates; it provides extra algorithmic 'tools' for efficiently coding interlaced video, supports a wide range of bit rates and provides for multichannel surround sound coding. This tutorial paper introduces the principles used for compressing video according to the MPEG-2 standard, outlines the general structure of a video coder and decoder, and describes the subsets ('profiles') of the toolkit and the sets of constraints on parameter values ('levels') defined to date.     

结合卷积神经网络的HEVC帧内编码压缩改进算法

近年来,卷积网络深度学习已在图像处理、目标检测等领域取得巨大成功。受其启发,将卷积神经网络(CNN)应用于传统视频压缩标准已成为一个新的研究热点。本文提出一种集成卷积神经网络的高效视频编码(HEVC)压缩改进算法,将下采样过程、HEVC的编解码过程、上采样及质量增强过程集成为一体。为高效提取视频帧的结构特征,在所提压缩算法中集成了两个卷积神经网络。提出了一种下采CNN(DwSCNN)代替双三次下采,在有效降低分辨率的同时保留细节信息,得到更为紧凑的低分辨率视频序列,将此低分辨率视频序列通过HEVC帧内编码进行进一步的数据量压缩,通过提出一个质量增强CNN(PPCNN)来改善解码后恢复到原始分辨率的降质视频序列。实验结果显示,本文压缩改进算法在低码率段与标准HEVC相比,能达到更好的质量重建,并且在接近一致的PSNR值时,能节省39.46%的时间和11.04%的比特率,本文算法的视频压缩性能优于HEVC标准算法和相关文献方法。     

Smartphones Apps Implementing a Heuristic Joint Coding for Video Transmissions over Mobile Networks

This paper presents the scheme Heuristic Application Layer Joint Coding (Heuristic-ALJC) for video transmissions aimed at adaptively and jointly varying both applied video compression and source encoding at the application layer used to protect video streams. Heuristic-ALJC includes also a simple acknowledgement based adaptation of the transmission rate and acts on the basis of feedback information about the overall network status estimated in terms of maximum allowable network throughput and link quality (lossiness). Heuristic-ALJC is implemented through two smartphone Apps (transmitter and receiver) and is suitable to be employed to transmit video streams over networks based on time varying and possibly lossy channels. A deep performance investigation, carried out through a real implementation of the Apps over Android smartphones, compares Heuristic-ALJC with static schemes.     

A Real-Time Video Decoder for Digital HDTV

In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.     

Lossless compression of video using temporal information

We consider the problem of lossless compression of video by taking into account temporal information. Video lossless compression is an interesting possibility in the line of production and contribution. We propose a compression technique which is based on motion compensation, optimal three-dimensional (3-D) linear prediction and context based Golomb-Rice (1966, 1979) entropy coding. The proposed technique is compared with 3-D extensions of the JPEG-LS standard for still image compression. A compression gain of about 0.8 bit/pel with respect to static JPEG-LS, applied on a frame-by-frame basis, is achievable at a reasonable computational complexity.