An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3$,times,$ 2.5 mm$^2$ . The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 $~$GHz$cdot$2$^{{rm SFDR}/6}$/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is ${-}$ 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.      

DAC欠采样实现高中频信号的直接合成

文章探讨了DAC在低于奈奎斯特率的采样率下合成高中频信号的方法,提出了通过后端的运放、高速电子开关以及延迟电路,利用单个DAC实现高中频信号一个周期内的双相位输出,在第二奈奎斯特域直接合成高中频信号的方法,并且对产生信号的频谱进行了分析,提出了补偿方案,给出了仿真与实验结果。     

Delta-Sigma Modulation for Direct Digital Frequency Synthesis

This paper compares different $DeltaSigma$ modulation techniques for direct digital frequency synthesis (DDS). $DeltaSigma$ modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-$mu$m CMOS technology with core area of $1.7times 2.1 {hbox {mm}}^{2}$ and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain $DeltaSigma$ modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward $DeltaSigma$ modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications.      

FPGA直接数字频率合成信号发生器

DDS是从相位的概念出发进行频率合成的一项新型技术。简要介绍了DDS的工作原理,提出了一种选用Altera公司不久前发布崭新体系的大容量Stratix II系列FPGA—EP2S60来实现DDS系统的核心部分的设计方案。并用Matlab语言将QUARTUSⅡ4.0波形仿真结果转换为波形曲线。实验结果表明,利用Altera公司的FPGA—EP2S60器件,通过各种优化措施,设计开发的DDS系统,达到了预期的目的,具有较高的性价比。     

实现数字三相波形合成的低价数字DAC

很多应用都涉及采用微控制器或DSP作数字控制的三相正弦波数字合成．如交流电机驱动器、有源功率滤波器,以及电网电压合成器。用普通模拟技术（参考文献1）或DDS（直接数字合成）就可以完成这种合成。数字技术有更高的稳定性．并且能包含对频率、相位和幅度的调节。对于需要16bit以上更高分辨率的应用,三相信号合成、DDS方法要使用微控制器或DSP与多个DAC接口。这种方法不仅要使用大量器件．并且还需要很多支持元件和电路板空间。尽管一个器件可以有4、8、32甚至更多的多输出串行控制的DAC,但DAC付出了多个通道的代价,得到的位数却不多。     

直接数字频率合成信号发生器的设计

简要介绍了基于现场可编程门阵列(FPGA)及直接频率合成信号发生器(DDS)技术的信号发生器设计和实现.该设计采用CycloneⅡ系列器件EP2C8Q208C8实现DDS波形产生电路、D/A转换器控制及与ARM接口等功能,用先进精简指令单片机(ARM) STM32F103进行频率控制字、相位控制字,频率输出显示等控制.由于FPGA的晶振是50 MHz,经过增强型锁相环(PLL)后采样频率可达到250 MHz,通过14位400MSPS的高速数模转换器(DAC)和7阶椭圆低通滤波器,最终输出的正弦波最大频率可达到70 MHz.     

A Heterogeneous 16-Bit DAC Using a Replica Compensation

A highly monotonic very low power 16-bit 2-MS/s digital-to-analog converter (DAC) for high-resolution control loop systems is proposed and demonstrated. Replica compensation is used in improving the monotonicity of a heterogeneous DAC composed of a coarse current steering DAC and a fine resistor-ladder DAC. A complete DAC, including an on-chip bandgap reference and an output buffer, consumes only 0.6 mA with a 2.7-V supply. The 2.19-mm $^{2}$ DAC with 10-I/O bonding pads implemented in 0.18- $mu$m Bi-CMOS process achieves ${pm} 0.8$ least significant bit (LSB) differential nonlinearity, ${pm} 4$ LSB integral nonlinearity, and ${pm} $ 3-mV offset error at 2-MS/s sample rate.      

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This enables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power.     

Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme

In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor’s expansion. This method only needs a lookup-table size of total bits, one multiplier, one n × 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS’s, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 μm cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.

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直接数字频率合成器(DDS)应用的频率规划

DDS基本知识与频率规划的意义 DDS被定义为是一种由固定频率参考时钟源产生正弦波的数字技术。需要注意的是,参考时钟源的动态性能会直接影响到DDS的输出频谱。DDS有如下优点：     

一种多通道直接数字频率合成器的设计

基于直接数字频率合成(DDS)的原理,设计实现了四通道的直接数字频率合成器。其内部集成四路DAC,最高工作频率达到500 MHz。分析实现相位幅度转换的CORDIC算法原理并进行算法改进,降低了整体电路的功耗。     

FPGA实现的直接数字频率合成器

描述了直接数字频率合成器（DDS）的原理和特点，并给出了用FPGA实现DDS的方法及仿真结果。     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,设计了一种采用分段式电流舵结构的高速高精度DAC.电路设计中同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响.电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能.     

一种高速直接数字频率合成器及其FPGA实现

介绍了一种用于QAM调制和解调的直接数字频率合成器,该电路同时输出10位正弦和余弦两种波形,系统时钟频率为50MHz,信号的谐波小于－72dB。输出信号的范围为DC到25MHz,信号频率步长为0．0116Hz,相应的转换速度为20ns,建立时间延迟为4个时种。直接数字合成器（DDFS）采用一种有效查找表的方式生成正弦函数,为了降低ROM的大小,采用了1／8正弦波形函数压缩算法。直接数字频率合成器的数字部分由Xilinx FPGA实现,最后通过数模转换器输出。     

DDS频谱杂散分析及其抑制研究

杂散特性是制约DDS（直接数字频率合成）技术进一步应用和发展的重要因素,其相位舍位、幅度量化和DAC（数模转换器）的非理想特性等是影响DDS输出频谱质量的主要杂散源。文中对DDS输出的理想频谱进行了分析,介绍了相位舍位、幅度量化和DAC的非理想特性等杂散源对DDS输出频谱质量的影响;针对杂散源对DDS输出频谱质量的影响,总结了抖动注入法、延时叠加法、数据压缩法等几种抑制杂散的方法,对DDS技术的工程应用具有参考价值。     

利用单片机和CPLD实现直接数字频率合成(DDS)

与传统的频率合成方法相比，DDS合成信号具有频率切换时间短，频率分辨率高，相位变化连续等诸多优点，使用单片机灵活的控制能力以及良好的人机对话功能与CPLD器件的高性能，高集成度相结合，可以克服传统DDS设计中的很多不足，从而设计开发出性能优良的DDS系统。     

A Low Voltage 14-Bit Self-Calibrated CMOS DAC with Enhanced Dynamic Linearity

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology. Saeed Saeedi was born in Tehran, Iran, in 1979. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran in 2001 and 2003, respectively. Since 2002, he has been working with Iran Microelectronics Research Center, IMRC. He is currently working toward the Ph.D. degree. His research interests include analog and digital integrated circuits for communication systems and high performance data converters. Saeid Mehrmanesh was born in Arak, Iran in 1976. He received the B.Sc. and M.Sc. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2002. From 2000, he has been working with Iran Microelectronics Research Center as an analog and mixed-mode and RF-IC design engineer. Since 2004, he has been a Ph.D. student at the University of Tehran. His research interests include analog to digital and digital to analog data converters, low voltage and low power CMOS circuits, telecommunication circuits, high speed serial links and RF circuits. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993.From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.This revised version was published online in May 2005 with corrections to the authors affiliations.     

一种12位双斜积分式A／D转换器

研究了一种高分辨率双斜积分式A/D转换器.通过理论分析和实验仿真,构造了一个采样速率为120 SPS、分辨率达12位的A/D转换器电路;给出了0.2%精度下采样值模数转换的仿真结果,并进行了分析,以验证这种电路结构的可行性及优势.     

一种12位开关电流型Σ-△调制器

开关电流电路（ＳＩ）是近年兴起的一种模拟电路。文中引用了新型的两步采样开关电流技术（Ｓ＾２Ｉ）,对该电路中减小时钟馈漏效应的几种方法进行了分析。利用差分平衡结构的Ｓ＾２Ｉ存储单元设计了平衡Ｓ＾２Ｉ积分器,并在此基础上设计出一种平衡差分结构的二阶∑－△调制器。该调制器能够完全与标准ＣＭＯＳ数字工艺兼容。利用标准１．２μｍ数字ＣＯＭＳ工艺的ＨＳＰＩＣＥ模型参数进行了分析,该电路信噪比达到７３．３ｄＢ,     

用于带数字校正12位40MS／s流水线ADC的MDAC电路及数模接口

设计了一个用于40 MHz采样率,12位精度流水线A/D转换器第一级的MDAC电路.该电路采用高增益带宽积的增益自举放大器,在3.5 pF负载电容下,可以在8 ns内稳定在最终值的0.01%;设计了低失调、低回踢噪声比较器.蒙特卡罗分析表明,失调电压小于7 mV.电路采用SMIC 0.35 μm/3.3 V CMOS工艺,用于一个带数字校正的流水线A/D转换器.在MDAC中加入一个D/A接口电路,可以在不引入过多模拟电路的前提下,配合数字校正部分完成其校正功能.