An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3$,times,$ 2.5 mm$^2$ . The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 $~$GHz$cdot$2$^{{rm SFDR}/6}$/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is ${-}$ 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.      

四通道12位带回读功能的高压DAC设计

基于0.8μm 40V BCD工艺,设计并实现了一款可工作于±15V电源电压的四通道12位DAC。电路由寄存器、R-2R电阻阵列和接成单位增益模式的运算放大器构成。实测结果显示,VDD= +15V,VSS= -15V,VLOGIC= +5V,VREFH= +10V,VREFL= -10V,负载RL=2kΩ,CL=100pF时,DAC的输出摆幅为-10V ~ +10V, DNL指标为±1.2LSB,INL指标为±1.5LSB。     

DAC欠采样实现高中频信号的直接合成

文章探讨了DAC在低于奈奎斯特率的采样率下合成高中频信号的方法,提出了通过后端的运放、高速电子开关以及延迟电路,利用单个DAC实现高中频信号一个周期内的双相位输出,在第二奈奎斯特域直接合成高中频信号的方法,并且对产生信号的频谱进行了分析,提出了补偿方案,给出了仿真与实验结果。     

Delta-Sigma Modulation for Direct Digital Frequency Synthesis

This paper compares different $DeltaSigma$ modulation techniques for direct digital frequency synthesis (DDS). $DeltaSigma$ modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-$mu$m CMOS technology with core area of $1.7times 2.1 {hbox {mm}}^{2}$ and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain $DeltaSigma$ modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward $DeltaSigma$ modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications.      

基于FPGA的低杂散直接数字频率合成器设计与实现

在分析了DDS其杂散来源及已有抑制方法的基础上,提出了一种新的有效抑制杂散的方法,经三角函数变换,将通常被舍掉的相位累加器输出的低B位利用起来.在Simulink中进行了仿真,结果显示在相位累加器位宽为32 bit,查找表寻址位数为12 bit时,较之未经优化的DDS,其杂散改善了60 dB.用Verilog语言设计实...     

内嵌14位DAC的高速直接数字频率合成器的设计

利用CORDIC算法实现相位幅度的转换;嵌入双路归零编码方式输出、电流源控制开关、14位DAC,成功设计了一种高速直接数字频率合成器.经0.18 μm 6M2P CMOS工艺流片,芯片面积为4.19 mm×3.17 mm,在1 GHz的工作频率下,输出信号在98.6 MHz处,SFDR为68.39 dB.     

FPGA直接数字频率合成信号发生器

DDS是从相位的概念出发进行频率合成的一项新型技术。简要介绍了DDS的工作原理,提出了一种选用Altera公司不久前发布崭新体系的大容量Stratix II系列FPGA—EP2S60来实现DDS系统的核心部分的设计方案。并用Matlab语言将QUARTUSⅡ4.0波形仿真结果转换为波形曲线。实验结果表明,利用Altera公司的FPGA—EP2S60器件,通过各种优化措施,设计开发的DDS系统,达到了预期的目的,具有较高的性价比。     

实现数字三相波形合成的低价数字DAC

很多应用都涉及采用微控制器或DSP作数字控制的三相正弦波数字合成．如交流电机驱动器、有源功率滤波器,以及电网电压合成器。用普通模拟技术（参考文献1）或DDS（直接数字合成）就可以完成这种合成。数字技术有更高的稳定性．并且能包含对频率、相位和幅度的调节。对于需要16bit以上更高分辨率的应用,三相信号合成、DDS方法要使用微控制器或DSP与多个DAC接口。这种方法不仅要使用大量器件．并且还需要很多支持元件和电路板空间。尽管一个器件可以有4、8、32甚至更多的多输出串行控制的DAC,但DAC付出了多个通道的代价,得到的位数却不多。     

A Heterogeneous 16-Bit DAC Using a Replica Compensation

A highly monotonic very low power 16-bit 2-MS/s digital-to-analog converter (DAC) for high-resolution control loop systems is proposed and demonstrated. Replica compensation is used in improving the monotonicity of a heterogeneous DAC composed of a coarse current steering DAC and a fine resistor-ladder DAC. A complete DAC, including an on-chip bandgap reference and an output buffer, consumes only 0.6 mA with a 2.7-V supply. The 2.19-mm $^{2}$ DAC with 10-I/O bonding pads implemented in 0.18- $mu$m Bi-CMOS process achieves ${pm} 0.8$ least significant bit (LSB) differential nonlinearity, ${pm} 4$ LSB integral nonlinearity, and ${pm} $ 3-mV offset error at 2-MS/s sample rate.      

直接数字频率合成信号发生器的设计

简要介绍了基于现场可编程门阵列(FPGA)及直接频率合成信号发生器(DDS)技术的信号发生器设计和实现.该设计采用CycloneⅡ系列器件EP2C8Q208C8实现DDS波形产生电路、D/A转换器控制及与ARM接口等功能,用先进精简指令单片机(ARM) STM32F103进行频率控制字、相位控制字,频率输出显示等控制.由于FPGA的晶振是50 MHz,经过增强型锁相环(PLL)后采样频率可达到250 MHz,通过14位400MSPS的高速数模转换器(DAC)和7阶椭圆低通滤波器,最终输出的正弦波最大频率可达到70 MHz.     

Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology

A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This enables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power.     

直接数字频率合成杂散抑制方法的研究

在理想条件下分析了直接数字频率合成（DDFS）输出信号的主频谱，在此基础上，引入了延时叠加法来减少其杂散分量，本文也讨论了DDFS线路中器件本身的非理想特性引起的量化噪声及减小量化噪声的方法，采用上述这些方法后，DDFS输出信号的频谱中的杂散和噪声得到了较大的改善，如要进一步抑制DDFS的杂散和噪声，则应考虑应用DDFS＋PLL方案。     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器（DDFS) . 为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland 技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩. 利用这些技术,ROM尺寸压缩了98%. 采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2. 在3.3V电源下,该芯片的功耗为167mW, 无杂散动态范围（SFDR）为61dB.     

数字射频存储器用DAC静态参数的表征与测试

分析并讨论了应用于相位体制数字射频存储器的DAC静态参数的表征方法.提出用时间非线性(TDNL和TINL)、幅度非线性(ADNL和AINL)以及相位非线性(PNL)来全面描述相位体制DAC的静态性能.仿真结果证明上述静态参数对DAC的频域性能有着显著影响,用它们表征相位体制DAC的静态性能是必要且可行的.采用上述方法对利用标准75mm GaAs MESFET全离子注入工艺流片得到的3bit相位体制DAC进行了低频静态测试,其静态参数优异,性能良好.     

Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme

In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor’s expansion. This method only needs a lookup-table size of total bits, one multiplier, one n × 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS’s, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 μm cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.

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数字射频存储器用DAC静态参数的表征与测试

分析并讨论了应用于相位体制数字射频存储器的DAC静态参数的表征方法．提出用时间非线性（TDNL和TINL）、幅度非线性（ADNL和AINL）以及相位非线性（PNL）来全面描述相位体制DAC的静态性能．仿真结果证明上述静态参数对DAC的频域性能有着显著影响，用它们表征相位体制DAC的静态性能是必要且可行的．采用上述方法对利用标准75mm GaAs MESFET全离子注入工艺流片得到的3bit相位体制DAC进行了低频静态测试，其静态参数优异，性能良好．     

直接数字频率合成器(DDS)应用的频率规划

DDS基本知识与频率规划的意义 DDS被定义为是一种由固定频率参考时钟源产生正弦波的数字技术。需要注意的是,参考时钟源的动态性能会直接影响到DDS的输出频谱。DDS有如下优点：     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,设计了一种采用分段式电流舵结构的高速高精度DAC.电路设计中同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响.电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能.     

FPGA实现的直接数字频率合成器

描述了直接数字频率合成器（DDS）的原理和特点，并给出了用FPGA实现DDS的方法及仿真结果。