An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits

Digital power supply noise is a key issue in the design of mixed-signal and radio frequency (RF) integrated circuits (IC). In this paper, we have evaluated the impact of different digital design alternatives and technological parameters on the noise power spectral density. Related rules guiding designers to minimise the effect of digital noise on the analogue RF section conclude the work.     

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-V_TH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-V_TH transistors in place of high-V_TH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-V_TH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.     

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits     

A current monitoring technique for IDDQ testing in digital integrated circuits

Although I_DDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that overcomes the current variations problem in I_DDQ testing is proposed. According to this, a core is partitioned into two subcircuits and the intrinsic leakage current of the one subcircuit is used to control the leakage current at the I_DDQ sensing node of the other and vice-versa during test application. This way process related leakage current variations are taken into account and small defective currents turn to be detectable according to the needs of modern nanometer technologies. Additionally, a Built-In Current Sensor is presented, which exploits the proposed technique and experimental results are illustrated by its application on a fabricated chip.     

数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.     

A speed, power, and supply noise evaluation of ECL driver circuits

We present an emitter coupled logic (ECL) active pull-down (APD) circuit which can provide a 10:1 ratio between active and inactive currents. The new APD circuit is compensated for variations in supply and temperature via a clamp voltage. The proposed circuit is evaluated by comparing its performance (in terms of speed, power dissipation, and generated supply noise) with the performance of five other driver circuits     

Importance of including power supply noise in digital circuitsimulations

Rapid fluctuations of power supply values, or switching noise, can have a significant effect on VLSI circuit speed. This is shown by comparing circuit simulations with measurements of the critical path delay of a self-resetting SRAM. It is shown that including the measured high frequency noise in the circuit simulation leads to very accurate prediction of circuit speed     

Built-in test for complex digital integrated circuits

A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).     

A manufacturing process for analog and digital gallium arsenide integrated circuits

A process for manufacturing small-to-medium scale GaAs integrated circuits is described. Integrated FET's, diodes, resistors, thin-film capacitors, and inductors are used for monolithic integration of digital and analog circuits. Direct implantation of Si into > 10⁵Ω.cm resistivity substrates produces n-layers with ± 10-percent sheet resistance variation. A planar fabrication process featuring retained anneal cap (SiO2), proton isolation, recessed Mo-Au gates, silicon nitride passivation, and a dual-level metal system with polyimide intermetal dielectric is described. Automated on-wafer testing at frequencies up to 4 GHz is introduced, and a calculator-controlled frequency domain test system described. Circuit yields for six different circuit designs are reported, and process defect densities are inferred.     

Impedance characteristics of power distribution grids in nanoscale integrated circuits

The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis difficult. The design of robust and area efficient power distribution networks for high-speed integrated circuits has therefore become a challenging task. The impedance characteristics of multilayer power distribution grids and the relevant design implications are the subject of this paper. The power distribution network spans many layers of interconnect with disparate electrical properties. Unlike single-layer grids, the electrical characteristics of multilayer grids vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low-resistance upper layers to the low-inductance lower layers. The inductance of a multilayer grid therefore decreases with frequency, while the resistance increases with frequency. The lower layers of multilayer power grids provide a low-inductance current path, significantly reducing the grid impedance at high frequencies. Multilayer power distribution grids extend to the lower interconnect layers, exhibiting superior high-frequency impedance characteristics as compared to power distribution grids built exclusively within the upper, low-resistance metal layers. A significant share of metal resources to distribute the global power should therefore be allocated to the lower metal layers. An analytic model is also presented to determine the impedance characteristics of a multilayer grid from the inductive and resistive properties of the comprising individual grid layers.     

A novel power plane with super-wideband elimination of ground bounce noise on high speed circuits

A novel L-bridged electromagnetic bandgap (EBG) power/ground planes is proposed with super-wideband suppression of the ground bounce noise (GBN) from 600Mz to 4.6GHz. The L-shaped bridge design on the EBG power plane not only broadens the stopband bandwidth, but also can increase the mutual coupling between the adjacent EBG cells by significantly decreasing the gap between the cells. It is found the small gap design can prevent from the severe degradation of the signal quality for the high-speed signal referring to the perforated EBG power plane. The excellent GBN suppression performance with keeping reasonably good signal integrity for the proposed structure is validated both experimentally and numerically. Good agreement is seen.     

A comprehensive view of digital integrated electronic circuits

The present generation of digital integrated circuits is based on the batch-fabrication of interconnected transistors and diodes. These circuits successfully provide the elementary logic modules which can be directly interconnected to realize complex digital systems. The basic circuit configurations and their design must fulfill the prime requirement of signal-quantization under various operational aspects; and thus they reflect compromises between the operation speed, the noise margin, the number of fan-in and fan-out, the operating temperature range, the power dissipation, and the cost of fabricating circuit components to the required tolerance.     

MOSFET thermal noise modeling for analog integrated circuits

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements     

A noise optimization technique for integrated low-noise amplifiers

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

Precision photonic integration for future large-scale photonic integrated circuits

Since the proposal of the concept of photonic integrated circuits (PICs), tremendous progress has been made. In 2005, Infinera Corp. rolled out the first commercial PICs, in which hundreds of optical functions were integrated onto a small form factor chip for wavelength division multiplexing (WDM) systems^[1], then a monolithically integrated 10 × 10 Gb/s WDM chip has been demonstrated, the channel number is ten^[2]. Like ICs, large-scale PICs (LS-PICs) will be sure to be pursued. However, there are still some general challenges associated with LS-PICs. The challenges for III–V (mainly InP) PICs is the semiconductor process, which is not mature for LS-PICs. Up to now, the channel number in commercial III–V WDM PICs by Infinera is still about ten or less. For silicon photonics, the challenge is the silicon based light source. The low cost and mature solution for silicon lasers is still unavailable and only 4 × 25 Gb/s PICs are deployed by Intel Corp. after 18-year R&;D investment. Thus it is still unavailable for practical LS-PICs in the present times.     

Ground bounce modelling for digital gigascale integrated circuits

In the paper, an analytical model for ground bounce noise evaluation taking into account the interdependence between I_DD switching current and V_DD noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. The main conclusion is that noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes and accurate analysis of two canonical circuits.     

集成电路低功耗设计方法

信息化的社会发展无法离开电子产品的不断进步,而其对其低功耗的设计要求正在不断增强.但当前电子产品的功能质量在提高的同时,其功耗设计却没能跟上设计的要求,一直处于上升趋势,这将对电子产品性能的提高产生一定的影响.一款经久耐用、性能强的电子产品必须具备水平相当的低功耗设计方式.本文主要探讨了集成电路的低功耗设计方法,以作为相关参考.