共查询到20条相似文献,搜索用时 109 毫秒
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应用于箭体各模块功能测试,对数据采集有特殊的技术指标,要求系统能读取大容量数据、误码率极低。基于此参考已有的压缩技术,设计了基于FPGA和DSP的数据采集与压缩系统,能够实现12路模拟信号的采集与处理,采样率为324 ksample/s。采用DSP对数据进行压缩,压缩去除率达到75%。针对采集数据误码问题,提出对数据分帧传输的设计方案。最后对系统进行了测试验证,实验表明系统性工作稳定、各项技术指标均达到要求。 相似文献
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为了能将日益应用广泛的Papervision3D、能在Flash Player中播放的目的,采用较为新颖的3D引擎方法,做了三维到二维的转换、Flint粒子系统实验,实现了平滑拉近物体从远处拉近及喷泉的效果.通用开源Flash 3D渲染引擎中Papervision3D是基于ActionScript的开源项目,而Flash在3D领域的应用相对贫乏,在Flash Player中播放,则具备体积小、与用户交互能力强、效果逼真的3D Web应用程序特点. 相似文献
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选用CineformReo3D和Dashwood FxFactory两款支持3D剪辑制作的软件,在苹果工作站及苹果平台上进行3D后期节目制作流程的测试,总结了测试结论。 相似文献
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介绍了一种MPEG-2编码电路MB86390A。该电路包括视、音频信号采集,编码和差分传输。它与解码电路组成的编、解码系统具有良好的性能。在3Mbps数据率时,与未经编码的视、音频信号质量基本相当;在1.5Mbps数据率时,肉眼可察觉到在极剧烈运动图像中的方块效应,视、音频整体效果仍令人满意。 相似文献
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《Signal Processing: Image Communication》2004,19(3):239-256
A multiview sequence CODEC with flexibility, MPEG-2 compatibility and view scalability is proposed. We define a GGOP (Group of GOP) structure as a basic coding unit to efficiently code multiview sequences. Our proposed CODEC provides flexible GGOP structures based on the number of views and baseline distances among cameras. The encoder generates two types of bitstreams; a main bitstream and an auxiliary one. The main bitstream is the same as a MPEG-2 mono-sequence bitstream for MPEG-2 compatibility. The auxiliary bitstream contains information concerning the remaining multiview sequences except for the reference sequences. Our proposed CODEC with view scalability provides several viewers with realities or one viewer motion parallax whereby changes in the viewer’s position results in changes in what is seen. The important point is that a number of view points are selectively determined at the receiver according to the type of display modes. The viewers can choose an arbitrary number of views by checking the information so that only the views selected are decoded and displayed.The proposed multiview sequence CODEC is tested with several multiview sequences to determine its flexibility, compatibility and view scalability. In addition, we subjectively confirm that the decoded bitstreams with view scalability can be properly displayed by several types of display modes, including 3D monitors. 相似文献
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This paper describes the performance of the MPEG-4 still texture image codec in coding noisy images. As will be shown, when using the MPEG-4 still texture image codec to compress a noisy image, increasing the compression rate does not necessarily imply reducing the peak-signal-to-noise ratio (PSNR) of the decoded image. An optimal operating point having the highest PSNR can be obtained within the low bit rate region. Nevertheless, the visual quality of the decoded noisy image at this optimal operating point is greatly degraded by the so-called "cross" shape artifact. In this paper, we analyze the reason for the existence of the optimal operating point and the "cross" shape artifact when using the MPEG-4 still texture image codec to compress noisy images. We then propose an adaptive thresholding technique to remove the "cross" shape artifact of the decoded images. It requires only a slight modification to the quantization process of the traditional MPEG-4 encoder while the decoder remains unchanged. Finally, an analytical study is performed for the selection and validation of the threshold value used in the adaptive thresholding technique. It is shown that, the visual quality and PSNR of the decoded images are much improved by using the proposed technique comparing with the traditional MPEG-4 still texture image codec in coding noisy images. 相似文献
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提出了一种汉明码译码器改进方法,采用串行数据传输和时序优化的方法来降低汉明码译码器占用的资源和成本,并采用模块式的设计方法,设计了编译码系统仿真平台,详细地阐述了整个系统和各个模块的FPGA实现过程.仿真结果表明,设计的译码器复杂度明显降低. 相似文献
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基于FPGA的多路E1信道的MPEG-2码流传输 总被引:1,自引:0,他引:1
阐述了多E1信道的复用、反向复用技术,并由此设计出了一种基于现场可编程门阵列(FPGA)的MPEG-2码流的多E1信道复用器、反向复用器电路。分析了FPGA具体实现过程中的一些常见问题,以及传输路由引起的多信道之间的信道时延差对接收端数据复用的影响。该设计实现了MPEG-2码流、控制码数据在多路E1信道中的透明传输,适配FPGA电路内置帧发生器和n(n=2,3,4)倍2.048MHz时钟发生器。 相似文献
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DVB系统中扰码发生器的FPGA实现 总被引:2,自引:1,他引:1
为了保证在任何情况下进入数字电视DVB传输系统的数据码流中"0"与"1"的概率都能基本相等,传输系统首先要用一个伪随机序列对输入的MPEG-2码流进行扰乱处理。给出了DVB标准中扰码发生器的FPGA设计方案,并以Altera公司的QuartusII为开发平台,运用Verilog语言描述了各部分设计并给出仿真结果。 相似文献
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基于FPGA的二维DCT变换的实现 总被引:7,自引:1,他引:6
二维离散余弦变换(DCT)在图像处理和视频编码中起重要的作用。以MPEG 2全I帧编码为背景,在现场可编程门阵列(FPGA)上实现8×8像素的二维DCT变换。算法首先把8×8像素的二维DCT变换化简成8次一维DCT变换加上适当的蝶形运算和顺序重排操作。试验表明,方案可以只用一个一维DCT模块实现输入采样率为74.25MHz的二维DCT变换。 相似文献
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数字信号处理模块中的串行RapidIO设计 总被引:1,自引:0,他引:1
RapidIO互连构架是一种基于可靠性的开放式标准,可应用于连接多处理器、存储器和通用计算机平台.本文基于集成双核处理器MPC8641D和FPGA芯片XC5VSX240T的数字信号处理平台,进行了串行RapidIO(SRIO)技术的开发.文中给出了SRIO互连架构的硬件设计方案以及MPC8641D中SRIO数据通信软件... 相似文献